ATtiny45 datasheet(37/196 Pages) ATMEL

37 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

Figure 8-2.

MCU Start-up, RESET Tied to V

Figure 8-3.

MCU Start-up, RESET Extended Externally

Table 8-1.

Power On Reset Specifications

Note:

1. Before rising the supply has to be between VPORMIN and VPORMAX to ensure Reset.

8.4

External Reset

An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer

than the minimum pulse width (see Table 8-1) will generate a reset, even if the clock is not run-

ning. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches

the Reset Threshold Voltage – V

RST – on its positive edge, the delay counter starts the MCU

after the Time-out period – t

TOUT – has expired.

Symbol

Parameter

Min

Typ

Max

Units

POT

Power-on Reset Threshold Voltage (rising)

1.1

1.4

1.7

Power-on Reset Threshold Voltage (falling)(1)

0.8

1.3

1.6

PORMAX

VCC Max. start voltage to ensure internal

Power-on Reset signal

0.4

VPORMIN

VCC Min. start voltage to ensure internal

Power-on Reset signal

-0.1

VCCRR

VCC Rise Rate to ensure Power-on Reset

0.01

V/ms

VRST

RESET Pin Threshold Voltage

0.1 V

0.9V

RESET

TIME-OUT

INTERNAL

RESET

TOUT

RST

PORMA

VCC

CCRR

PORMIN

RESET

TIME-OUT

INTERNAL

RESET

tTOUT

VRST

VCC

POT

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