ATtiny45 datasheet(83/196 Pages) ATMEL

83 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

Figure 14-3. Timer/Counter1 Block Diagram

Three status flags (overflow and compare matches) are found in the Timer/Counter Interrupt

Flag Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1

and GTCCR. The interrupt enable/disable settings are found in the Timer/Counter Interrupt

Mask Register - TIMSK.

The Timer/Counter1 contains three Output Compare Registers, OCR1A, OCR1B, and OCR1C

as the data source to be compared with the Timer/Counter1 contents. In normal mode the Out-

put Compare functions are operational with all three output compare registers. OCR1A

determines action on the OC1A pin (PB1), and it can generate Timer1 OC1A interrupt in normal

mode and in PWM mode. Likewise, OCR1B determines action on the OC1B pin (PB3) and it can

generate Timer1 OC1B interrupt in normal mode and in PWM mode. OCR1C holds the

Timer/Counter maximum value, i.e. the clear on compare match value. In the normal mode an

overflow interrupt (TOV1) is generated when Timer/Counter1 counts from $FF to $00, while in

the PWM mode the overflow interrupt is generated when Timer/Counter1 counts either from $FF

to $00 or from OCR1C to $00. The inverted PWM outputs OC1A and OC1B are not connected in

normal mode.

In PWM mode, OCR1A and OCR1B provide the data values against which the Timer Counter

value is compared. Upon compare match the PWM outputs (OC1A, OC1A, OC1B, OC1B) are

generated. In PWM mode, the Timer Counter counts up to the value specified in the output com-

pare register OCR1C and starts again from $00. This feature allows limiting the counter “full”

value to a specified value, lower than $FF. Together with the many prescaler options, flexible

PWM frequency selection is provided. Table 14-6 lists clock selection and OCR1C values to

obtain PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz

in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution.

8-BIT DATABUS

TIMER INT. FLAG

TIMER/COUNTER1

8-BIT COMPARATOR

T/C1 OUTPUT

COMPARE REGISTER

TIMER INT. MASK

TIMER/COUNTER1

(TCNT1)

T/C CLEAR

T/C1 CONTROL

LOGIC

PCK

T/C1 OVER-

FLOW IRQ

T/C1 COMPARE

MATCH B IRQ

OC1A

(PB1)

T/C1 COMPARE

MATCH A IRQ

T/C CONTROL

(OCR1A)

(OCR1B)

(OCR1C)

8-BIT COMPARATOR

T/C1 OUTPUT

COMPARE REGISTER

8-BIT COMPARATOR

T/C1 OUTPUT

COMPARE REGISTER

GLOBAL T/C CONTROL

OC1A

(PB0)

OC1B

(PB4)

OC1B

(PB3)

DEAD TIME GENERATOR

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