ATtiny45 datasheet(88/196 Pages) ATMEL

88 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

• Bit 4– OCIE0A: Timer/Counter Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match A interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter occurs, i.e., when the OCF0A bit is set in the Timer/Counter

Interrupt Flag Register – TIFR0.

• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counte

Interrupt Flag Register – TIFR0.

• Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is

executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the

Timer/Counter Interrupt Flag Register - TIFR.

• Bit 0 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

14.1.8

Timer/Counter Interrupt Flag Register - TIFR

• Bit 7 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

• Bit 6 - OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A

are set (one), the Timer/Counter1 A compare match interrupt is executed.

• Bit 5 - OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1B - Output Compare Register 1A. OCF1B is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B

are set (one), the Timer/Counter1 B compare match interrupt is executed.

• Bit 2 - TOV1: Timer/Counter1 Overflow Flag

In normal mode (PWM1A=0 and PWM1B=0) the bit TOV1 is set (one) when an overflow occurs

in Timer/Counter1. The bit TOV1 is cleared by hardware when executing the corresponding

interrupt handling vector. Alternatively, TOV1 is cleared, after synchronization clock cycle, by

writing a logical one to the flag.

Bit

$38 ($58)

-OCF1A

OCF1B

OCF0A

OCF0B

TOV1

TOV0

TIFR

Read/Write

R/W

Initial value

ATtiny45 Datenblatt(PDF) 88 Page - ATMEL Corporation

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