ATtiny45 datasheet(60/196 Pages) ATMEL

60 / 196 page

7598H–AVR–07/09

ATtiny25/45/85

11.3

General Interrupt Flag Register – GIFR

• Bits 7, 4..0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 6 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set

(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

• Bit 5 – PCIF: Pin Change Interrupt Flag

When a logic change on any PCINT5..0 pin triggers an interrupt request, PCIF becomes set

(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it.

11.4

Pin Change Mask Register – PCMSK

• Bits 7, 6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bits 5..0 – PCINT5..0: Pin Change Enable Mask 5..0

Each PCINT5..0 bit selects whether pin change interrupt is enabled on the corresponding I/O

pin. If PCINT5..0 is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the

corresponding I/O pin. If PCINT5..0 is cleared, pin change interrupt on the corresponding I/O pin

is disabled.

Bit

543

–

INTF0

PCIF

––

–

GIFR

Read/Write

R/W

Initial Value

Bit

–

PCINT5

PCINT4

PCINT3

PCINT2

PCINT1

PCINT0

PCMSK

Read/Write

R/W

Initial Value

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