ATtiny45 datasheet(132/196 Pages) ATMEL

132 / 196 page

132

7598H–AVR–07/09

ATtiny25/45/85

20.4.1

Store Program Memory Control and Status Register – SPMCSR

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Program memory operations.

• Bits 7..5 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and always read as zero.

• Bit 4 – CTPB: Clear Temporary Page Buffer

If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be

cleared and the data will be lost.

• Bit 3 – RFLB: Read Fuse and Lock Bits

An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register,

will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destina-

tion register. See “EEPROM Write Prevents Writing to SPMCSR” on page 133 for details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Write, with the data stored in the temporary buffer. The page address is

taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit

will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four

clock cycles. The CPU is halted during the entire Page Write operation.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The

data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,

or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire

Page Write operation.

• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special

meaning, see description above. If only SPMEN is written, the following SPM instruction will

store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of

the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,

or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write,

the SPMEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower

five bits will have no effect.

Bit

210

–

CTPB

RFLB

PGWRT

PGERS

SPMEN

SPMCSR

Read/Write

R/W

Initial Value

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