SPRUG18 datasheet(54/214 Pages) TI

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TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

www.ti.com

Not all masters on the C6474 DSP may connect to slaves. Allowed connections are summarized in

Table 4-1 and Table 4-2.

SCR A is the main 128-bit switch fabric, which includes the slave ports of all C64x+ Megamodules. There

are three dedicated, 128-bit TPTC channels for internal memory-to-memory transfers, though the channels

can be used to access anything on SCR B as well. Note that any module accessing these particular

C64x+ Megamodules ports, including the EDMA, must use the global addresses, not the local addresses.

The Antenna Interface (AIF) is connected to the SCR via a special bridge that separates the read and

write interfaces into individual ports. The AIF is fully accessible to TPTC channels 3, 4, and 5, allowing

antenna data to be transferred between the AIF and any DSP memory.

Two of the SCR slave ports are driven by masters from SCR B, allowing data to be transferred between

the device peripherals and L2 memory.

Table 4-1. SCR A Connection Matrix

C64x+

SCR B (Br4)

SCR B (Br5)

AIF (Br22)

MEGAMODULE

CORE 0

CORE 1

CORE 2

SCR B (Br2)

SCR B (Br3)

TPTC3-RM

TPTC3-WM

TPTC4-RM

TPTC4-WM

TPTC5-RM

TPTC5-WM

SCR B is a secondary, 64-bit switch fabric, primarily dedicated to slave peripherals that require servicing

by the TPDMA. Additionally, master peripherals that are sub-128 bit are connected to this switch fabric.

There are two master ports on the SCR that allow masters to send commands to any of the slaves on

SCR A. There are three TPTC channels directly connected to SCR B to service the slave peripherals.

The Ethernet MAC (EMAC) is connected to the switch fabric with a pair of bridges to convert from VBUSP

to VBUSM (Br 6), along with a change in the bus width and frequency (Br 7). The Br 7 handles a majority

of this conversion, with the Br 6 bridge serving as a protocol-conversion gasket.

The RapidIO CPPI port is connected to the switch fabric similarly to the EMAC connection. This enables

RapidIO to use L2 or DDR2 for buffer descriptors. RapidIO is connected directly to the switch fabric and

can master any memory.

The DDR EMIF is also directly connected as a slave, allowing any master full access to the external

memory space.

System Interconnect

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