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SPRUG18 Datenblatt(PDF) 64 Page - Texas Instruments |
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SPRUG18 Datenblatt(HTML) 64 Page - Texas Instruments |
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64 / 214 page ![]() TMS320C6474 SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 5-7. Megamodule Revision ID Register (MM_REVID) Field Descriptions BIT FIELD VALUE DESCRIPTION 31:16 VERSION 3H Version of the C64x+ Megamodule implemented on the device. This field is always read as 3h. 15:0 REVISION Revision of the C64x+ Megamodule version implemented on the device. The C64x+ Megamodule revision is dependent on the silicon revision being used. 5.8 C64X+ Megamodule Register Description(s) In some applications, some specific addresses may need to be read from their physical locations each time they are accessed (e.g., a status register within FPGA). The L2 controller offers registers that control whether certain ranges of memory are cacheable and whether one or more requestors are actually permitted to access these ranges. The registers are referred to as memory attribute registers (MARs). A list of MARs is provided in Table 5-12. Table 5-8. Megamodule Interrupt Registers HEX ADDRESS ACRONYM REGISTER NAME 0180 0000 EVTFLAG0 Event Flag Register 0 (Events [31:0]) 0180 0004 EVTFLAG1 Event Flag Register 1 0180 0008 EVTFLAG2 Event Flag Register 2 0180 000C EVTFLAG3 Event Flag Register 3 0180 0010 - 0180 001C - Reserved 0180 0020 EVTSET0 Event Set Register 0 (Events [31:0]) 0180 0024 EVTSET1 Event Set Register 1 0180 0028 EVTSET2 Event Set Register 2 0180 002C EVTSET3 Event Set Register 3 0180 0030 - 0180 003C - Reserved 0180 0040 EVTCLR0 Event Clear Register 0 (Events [31:0]) 0180 0044 EVTCLR1 Event Clear Register 1 0180 0048 EVTCLR2 Event Clear Register 2 0180 004C EVTCLR3 Event Clear Register 3 0180 0050 - 0180 007C - Reserved 0180 0080 EVTMASK0 Event Mask Register 0 (Events [31:0]) 0180 0084 EVTMASK1 Event Mask Register 1 0180 0088 EVTMASK2 Event Mask Register 2 0180 008C EVTMASK3 Event Mask Register 3 0180 0090 - 0180 009C - Reserved 0180 00A0 MEVFLAG0 Masked Event Flag Status Register 0 (Events [31:0]) 0180 00A4 MEVFLAG1 Masked Event Flag Status Register 1 0180 00A8 MEVFLAG2 Masked Event Flag Status Register 2 0180 00AC MEVFLAG3 Masked Event Flag Status Register 3 0180 00B0 - 0180 00BC - Reserved 0180 00C0 EXPMASK0 Exception Mask Register 0 (Events [31:0]) 0180 00C4 EXPMASK1 Exception Mask Register 1 0180 00C8 EXPMASK2 Exception Mask Register 2 0180 00CC EXPMASK3 Exception Mask Register 3 0180 00D0 - 0180 00DC - Reserved 0180 00E0 MEXPFLAG0 Masked Exception Flag Register 0(Events [31:0]) 0180 00E4 MEXPFLAG1 Masked Exception Flag Register 1 0180 00E8 MEXPFLAG2 Masked Exception Flag Register 2 0180 00EC MEXPFLAG3 Masked Exception Flag Register 3 64 C64x+ Megamodule Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TMS320C6474 |
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