SPRUG18 datasheet(80/214 Pages) TI

80 / 214 page

TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

www.ti.com

7.5

Enhanced Direct Memory Access (EDMA3) Controller

The primary purpose of the EDMA3 is to service user-programmed data transfers between two

memory-mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers

(e.g., data movement between external memory and internal memory), performs sorting or subframe

extraction of various data structures, services event driven peripherals such as a McBSP port, and

offloads data transfers from the device CPU.

The EDMA3 includes the following features:

•

Fully orthogonal transfer description

– 3 transfer dimensions: array (multiple bytes), frame (multiple arrays), and block (multiple frames)

– Single event can trigger transfer of array, frame, or entire block

– Independent indexes on source and destination

•

Flexible transfer definition:

– Increment or FIFO transfer addressing modes

– Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous

transfers, all with no CPU intervention

– Chaining allows multiple transfers to execute with one event

•

256 PaRAM entries

– Used to define transfer context for channels

– Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry

•

64 DMA channels

– Manually triggered (CPU writes to channel controller register), external event triggered, and chain

triggered (completion of one transfer triggers another)

•

8 Quick DMA (QDMA) channels

– Used for software-driven transfers

– Triggered upon writing to a single PaRAM set entry

•

6 transfer controllers and 6 event queues with programmable system-level priority

•

Interrupt generation for transfer completion and error conditions

•

Debug visibility

– Queue watermarking/threshold allows detection of maximum usage of event queues

– Error and status recording to facilitate debug

Each of the transfer controllers has a direct connection to the switched central resource (SCR). Table 4-1

lists the peripherals that can be accessed by the transfer controllers.

Peripheral Information and Electrical Specifications

Submit Documentation Feedback

Product Folder Link(s) :TMS320C6474

SPRUG18 Datenblatt(PDF) 80 Page - Texas Instruments

SPRUG18 Datenblatt(HTML) 80 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL