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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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SPRUG18 Datenblatt(PDF) 81 Page - Texas Instruments |
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SPRUG18 Datenblatt(HTML) 81 Page - Texas Instruments |
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81 / 214 page  TMS320C6474 www.ti.com SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 7.5.1 EDMA3 Channel Synchronization Events The EDMA3 supports up to 64 DMA channels that can be used to service system peripherals and to move data between system memories. DMA channels can be triggered by synchronization events generated by system peripherals. Table 7-4 lists the source of the synchronization event associated with each of the DMA channels. The association of each synchronization event and DMA channel is fixed and cannot be reprogrammed. Additional events are available to the EDMA3 via an external interrupt controller. For more details on Chip Interrupt Controller 3 (CIC3), see Section 7.6.2. Table 7-4. EDMA3 Channel Synchronization Events(1) EVENT CHANNEL EVENT EVENT DESCRIPTION 0 TINT0L Timer Interrupt Low 1 TINT0H Timer Interrupt High 2 TINT1L Timer Interrupt Low 3 TINT1H Timer Interrupt High 4 TINT2L Timer Interrupt Low 5 TINT2H Timer Interrupt High 6 CIC3_EVT0 CIC_EVT_o [0] from Chip Interrupt Controller 7 CIC3_EVT1 CIC_EVT_o [1] from Chip Interrupt Controller 8 CIC3_EVT2 CIC_EVT_o [2] from Chip Interrupt Controller 9 CIC3_EVT3 CIC_EVT_o [3] from Chip Interrupt Controller 10 CIC3_EVT4 CIC_EVT_o [4] from Chip Interrupt Controller 11 CIC3_EVT5 CIC_EVT_o [5] from Chip Interrupt Controller 12 XEVT0 McBSP 0 Transmit Event 13 REVT0 McBSP 0 Receive Event 14 XEVT1 McBSP 1 Transmit Event 15 REVT1 McBSP 1Receive Event 16 FSEVT4 Frame Synchronization Event 4 17 FSEVT5 Frame Synchronization Event 5 18 FSEVT6 Frame Synchronization Event 6 19 FSEVT7 Frame Synchronization Event 7 20 FSEVT8 Frame Synchronization Event 8 21 FSEVT9 Frame Synchronization Event 9 22 FSEVT10 Frame Synchronization Event 10 23 FSEVT11 Frame Synchronization Event 11 24 FSEVT12 Frame Synchronization Event 12 25 FSEVT13 Frame Synchronization Event 13 26 CIC3_EVT6 CIC_EVT_o [6] from Chip Interrupt Controller 27 CIC3_EVT7 CIC_EVT_o [7] from Chip Interrupt Controller 28 VCPREVT VCP Receive Event 29 VCPXEVT VCP Transmit Event 30 TCPREVT TCP Receive Event 31 TCPXEVT TCP Transmit Event 32 SEMINT0 Semaphore Interrupt 0 33 SEMINT1 Semaphore Interrupt 1 34 SEMINT2 Semaphore Interrupt 2 35 - Reserved 36 AIF_EVT0 AIF CPU Interrupt 0 37 AIF_EVT1 AIF CPU Interrupt 1 (1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the manual event set or transfer completion events. Copyright © 2008–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 81 Submit Documentation Feedback Product Folder Link(s) :TMS320C6474 |
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