SPRUG18 datasheet(77/214 Pages) TI

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TMS320C6474

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SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

Some peripherals can be statically powered down at device reset through the device configuration pins

(see Section 3.1, Device Configuration at Device Reset). Once in a static power-down state, the peripheral

is held in reset and its clock is turned off. Peripherals cannot be enabled once they are in a static

power-down state. To take a peripheral out of the static power-down state, a device reset must be

executed with a different configuration pin setting.

After device reset, all peripherals on the C6474 device are in a disabled state and must be enabled by

software before being used. It is possible to enable only the peripherals needed by the application while

keeping the rest disabled. Note that peripherals in a disabled state are held in reset with their clocks

gated. For more information on how to enable peripherals, see Section 3.2, Peripheral Selection After

Device Reset.

Peripherals used for booting, like I2C, are automatically enabled after device reset. It is possible to disable

peripherals used for booting after the boot process is complete. This, too, results in gating of the clock(s)

to the powered-down peripheral. Once a peripheral is powered-down, it must remain powered down until

the next device reset.

The C64x+ Megamodule also allows for software-driven power-down management for all of the C64x+

Megamodule components through its Power-Down Controller (PDC). The CPU can power-down part or

the entire C64x+ Megamodule through the power-down controller based on its own execution thread or in

response to an external stimulus from a host or global controller. More information on the power-down

features of the C64x+ Megamodule can be found in the TMS320C64x+ Megamodule Reference Guide

(literature number SPRU871).

Table 7-2 lists the Power/Sleep Controller (PSC) registers.

Table 7-2. Power/Sleep Controller Registers

HEX ADDRESS

ACRONYM

02AC 0000

PID

Peripheral Revision and Class Information

02AC 0120

PTCMD

Power Domain Transition Command Register

02AC 0128

PTSTAT

Power Domain Transition Status Register

02AC 0200

PDSTAT

Power Domain Status Register

02AC 0300

PDCTL0

Power Domain Control Register 0 (AlwaysOn)

02AC 0304

PDCTL1

Power Domain Control Register 1 (Antenna Interface)

02AC 0308

PDCTL2

Power Domain Control Register 2 (Serial RapidIO)

02AC 030C

Reserved

02AC 0310

PDCTL4

Power Domain Control Register 4 (TCP)

02AC 0314

PDCTL5

Power Domain Control Register 5 (VCP)

02AC 0800

Reserved

02AC 0804

Reserved

02AC 0808

Reserved

02AC 080C

MDSTAT3

Module Status Register 3 (C64x+ Core 0)

02AC 0810

MDSTAT4

Module Status Register 4 (C64x+ Core 1)

02AC 0814

MDSTAT5

Module Status Register 5 (C64x+ Core 2)

02AC 0818

MDSTAT6

Module Status Register 6 (Antenna Interface)

02AC 081C

MDSTAT7

Module Status Register 7 (Serial RapidIO)

02AC 0820

Reserved

02AC 0824

MDSTAT9

Module Status Register 9 (TCP)

02AC 0828

MDSTAT10

Module Status Register 10 (VCP)

02AC 082C

MDSTAT11

Module Status Register 11 (Never Gated)

02AC 0A00

Reserved

02AC 0A04

Reserved

02AC 0A08

Reserved

Peripheral Information and Electrical Specifications

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