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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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SPRUG18 Datenblatt(PDF) 60 Page - Texas Instruments |
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SPRUG18 Datenblatt(HTML) 60 Page - Texas Instruments |
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60 / 214 page  L1D Mode Bits 000 001 010 011 100 L1D Memory Block Base Address 00F0 0000 1/2 SRAM 16K bytes 00F0 4000 3/4 SRAM 8K bytes 00F0 6000 7/8 SRAM 4K bytes 00F0 7000 All SRAM Cache Cache Cache Cache 4K bytes 00F0 8000 L2ModeBits 010 011 100 L2Memory BlockBase Address 00800000 75% SRAM 768Kbytes 87.5% SRAM 128Kbytes 008C0000 93.75% SRAM 64Kbytes 008E0000 32Kbytes 008F0000 Cache 6.25% Cache 12.5% Cache 25% 008F8000 32Kbytes 000 001 96.875% SRAM 100% All SRAM Cache 3.125% TMS320C6474 SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Figure 5-3. TMS320C6474 L1D Memory Configurations Each core has 1024K bytes of local L2 RAM, with up to 256KB configurable as cache. The following figure provides the possible memory maps for the local L2. The L2 memory is typically shared across the two unified memory access ports (UMAP0 and UMAP1). The L2 SRAM begins at the same address. Figure 5-4. L2 Memory Configuration 1024KB All memory on the device has a unique location in the memory (see Section 2.3, Memory Map Summary). Global addresses that are accessible to all masters in the system are in all memory local to the processors. Additionally, local memory can be accessed directly by the associated processor through aliased addresses, where the eight MSBs are masked to zero. The aliasing is handled within the C64x+ Megamodule and allows for common code to be run unmodified on multiple cores. For example, address 60 C64x+ Megamodule Copyright © 2008–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s) :TMS320C6474 |
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