SPRUG18 datasheet(76/214 Pages) TI

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DD18

REFSSTL

DD11

POR

TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

www.ti.com

7.2

Recommended Clock and Control Signal Transition Behavior

All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic

manner.

7.3

Power Supplies

7.3.1

Power-Supply Sequencing

Power supply sequencing must be followed as seen in Figure 7-4.

Table 7-1. Timing Requirements for Power Supply Ramping

(see Figure 7-4)

NO.

PARAMETERS

MIN

MAX

UNIT

tsu(DVDD18-DVDD11)

Setup Time, DVDD18 and VREFSSTL supply stable before

0.5

200

DVDD11 and CVDD11 supplies stable

(1)

th(DVDD11-POR)

Hold time, POR low after CVDD11 and DVDD11 supplies stable

(1)

100

μs

(1)

Stable means that the voltage is valid as per Section 6.2, Recommended Operating Conditions.

Figure 7-4. Power-Supply Timing

For more information on power-supply sequencing, see the TMS320C6474 Hardware Design Guide

application report (literature number SPRAAW7)

7.3.2

Power-Supply Decoupling

In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as

possible close to the DSP. These caps need to be close to the DSP, no more than 1.25 cm maximum

distance to be effective. Physically smaller caps are better, such as 0402, but need to be evaluated from a

yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the decoupling

capacitors, therefore physically smaller capacitors should be used while maintaining the largest available

capacitance value. As with the selection of any component, verification of capacitor availability over the

product's production lifetime should be considered.

7.3.3

Power-Down Operation

One of the power goals for the C6474 device is to reduce power dissipation due to unused peripherals.

There are different ways to power down peripherals on the C6474 device.

Peripheral Information and Electrical Specifications

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