SPRUG18 datasheet(16/214 Pages) TI

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TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

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Table 2-3. C6474 Supported Boot Modes

MODE NAME

BOOTMODE[3:0]

DESCRIPTION

No Boot

0000b

No Boot (BOOTMODE[3:0] = 0000b)

I2C Master Boot A

0001b

Slave I2C address is 0x50. C64x+ Megamodule Core 0 configures I2C, acts as a

master to the I2C bus and copies data from an I2C EEPROM or a device acting as an

I2C slave to the DSP using a predefined boot table format. The destination address

and length are contained within the boot table. After boot table copy is complete, the

C64x+ Megamodule Core 0 brings the other C64x+ Megamodule Cores out of reset

by setting to 1 the EVTPULSE4 bit (bit 4) of the C64x+ Megamodule Core EVTASRT

I2C Master Boot B

0010b

Similar to I2C boot A except the slave I2C address is 0x51.

I2C Slave Boot

0011

The C64x+ Megamodule Core 0 configures I2C and acts as a slave and will accept

data and code section packets through the I2C interface. It is required that an I2C

master in present in the system.

EMAC Master Boot

0100b

TI Ethernet Boot, C64x+ Megamodule Core 0 configures EMAC0 and EDMA, if

required, and brings the code image into the internal on-chip memory via the protocol

EMAC Slave Boot

0101b

defined by the boot method (EMAC bootloader). After initializing the on-chip memory

EMAC Forced-Mode Boot

0110b

to the known state, C64x+ Megamodule Core 0 brings the other C64x+ Megamodule

Cores out of reset.

Reserved

0111b

Reserved

Serial RapidIO Boot (Config 0)

1000b

The C64x+ Megamodule Core 0 configures the SRIO and an external host loads the

application via SRIO peripheral, using directIO protocol. A doorbell interrupt is used to

Serial RapidIO Boot (Config 1)

1001b

indicate that the code has been loaded. For more details on the Serial RapidIO

Serial RapidIO Boot (Config 2)

1010b

configurations, see Table 2-4.

Serial RapidIO Boot (Config 3)

1011b

C64x+ Megamodule Core 0 configures Serial RapidIO and EDMA, if required, and brings the code image

into the internal on-chip memory via the protocol defined by the boot method (SRIO bootloader) and then

C64x+ Megamodule Core 0 brings the other C64x+ Megamodule Cores out of reset. Note that SRIO boot

modes are only supported on port 0.

Table 2-4. Serial RapidIO (SRIO) Supported Boot Modes

SRIO BOOT MODE

SERDES CLOCK

LINK RATE

BOOTMODE[3:0]

Bootmode 8 - Config 0

125 MHz

1.25 Gbps

1000b

Bootmode 9 - Config 1

125 MHz

3.125 Gbps

1001b

Bootmode 10 - Config 2

156.25 MHz

1.25 Gbps

1010b

Bootmode 11 - Config 3

156.25 MHz

3.125 Gbps

1011b

All the other BOOTMODE[3:0] modes are reserved.

2.4.2

Second-Level Bootloaders

Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader

allows for any level of customization to current boot methods as well as the definition of a completely

customized boot.

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