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SPRUG18 Datenblatt(PDF) 75 Page - Texas Instruments |
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SPRUG18 Datenblatt(HTML) 75 Page - Texas Instruments |
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75 / 214 page ![]() TransmissionLine DDR2OutputTestLoad Z0=50 W DataSheetTiming ReferencePoint DevicePin (A) Device 4pf TransmissionLine OutputTestLoadExcludingDDR2 Z0=50 W Device 5pf Vref=0.9V V =V MIN(orV MIN) ref IH OH V =V MAX(orV MAX) ref IL OL TMS320C6474 www.ti.com SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 7 Peripheral Information and Electrical Specifications 7.1 Parameter Information A. The data sheet provides timing at the device pin. For output analysis, the transmission line and associated parasitics (vias, multiple nodes, etc.) must also be taken into account. The transmission line delay varies depending on the trace length. An approximate range for output delays can vary from 176 ps to 2 ns depending on the end product design. For recommended transmission line lengths, see the appropriate application notes, user 's guides, and design guides. A transmission line delay of 2 ns was used for all output measurements, except the DDR2 which was evaluated using a 528-ps delay. B. This figure represents all outputs, except differential or I2C. Figure 7-1. Test Load Circuit for AC Timing Measurements The load capacitance value stated is for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. 7.1.1 1.8 V Signal Transition Levels All input and output timing parameters are referenced to 0.9 V for both "0" and "1" logic levels. Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements All rise and fall transition timing parameters are reference to VIL MAX and VIH MIN for input clocks. Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels Copyright © 2008–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 75 Submit Documentation Feedback Product Folder Link(s) :TMS320C6474 |
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