SPRUG18 datasheet(172/214 Pages) TI

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TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

www.ti.com

7.18 Serial RapidIO (SRIO) Port

The SRIO Port on the C6474 device is a high-performance, low pin-count interconnect aimed for

embedded markets. RapidIO is based on the memory and device addressing concepts of processor buses

where the transaction processing is managed completely by hardware. This enables the RapidIO

interconnect to lower the system cost by providing lower latency, reduced overhead of packet data

processing, and higher system bandwidth, all of which are key for wireless interfaces. The RapidIO

interconnect offers very low pin-count interfaces with scalable system bandwidth based on 10-Gigabit per

second (Gbps) bidirectional links.

The PHY part of the RIO consists of the physical layer and includes the input and output buffers (each

serial link consists of a differential pair), the 8-bit/10-bit encoder/decoder, the PLL clock recovery, and the

parallel-to-serial/serial-to-parallel converters.

The RapidIO interface should be designed to operate at a data rate up to 3.125 Gbps per differential pair.

7.18.1 SRIO Device-Specific Information

The approach to specifying interface timing for the SRIO Port is different than on other interfaces such as

McBSP. For these other interfaces the device timing was specified in terms of data manual specifications

and I/O buffer information specification (IBIS) models.

For the SRIO Port, Texas Instruments (TI) provides a printed circuit board (PCB) solution showing two

DSPs connected via a 1x SRIO link directly to the user. TI has performed the simulation and system

characterization to ensure all SRIO interface timings in this solution are met. The complete SRIO system

solution is documented in the TMS320C6474 DSP SERDES Implementation Guidelines application report

(literature number SPRAAW9).

TI only supports designs that follow the board design guidelines outlined in the SPRAAW9

application report.

The Serial RapidIO peripheral is a master peripheral in the C6474 DSP. It conforms to the RapidIO

™

Interconnect Specification, Part VI: Physical Layer 1x/4x LP-Serial Specification, Revision 1.2.

7.18.2 SRIO Register Description(s)

Table 7-79. RapidIO Control Registers

HEX ADDRESS

ACRONYM

02D0 0000

RIOPID

RapidIO Peripheral Identification Register

02D0 0004

RIO_PCR

RapidIO Peripheral Control Register

02D0 0008 - 02D0 001C

Reserved

02D0 0020

RIO_PER_SET_CNTL

RapidIO Peripheral Settings Control Register

02D0 0024 - 02D0 002C

Reserved

02D0 0030

RIO_GBL_EN

RapidIO Peripheral Global Enable Register

02D0 0034

RIO_GBL_EN_STAT

RapidIO Peripheral Global Enable Status Register

02D0 0038

RIO_BLK0_EN

RapidIO Block0 Enable Register

02D0 003C

RIO_BLK0_EN_STAT

RapidIO Block0 Enable Status Register

02D0 0040

RIO_BLK1_EN

RapidIO Block1 Enable Register

02D0 0044

RIO_BLK1_EN_STAT

RapidIO Block1 Enable Status Register

02D0 0048

RIO_BLK2_EN

RapidIO Block2 Enable Register

02D0 004C

RIO_BLK2_EN_STAT

RapidIO Block2 Enable Status Register

02D0 0050

RIO_BLK3_EN

RapidIO Block3 Enable Register

02D0 0054

RIO_BLK3_EN_STAT

RapidIO Block3 Enable Status Register

02D0 0058

RIO_BLK4_EN

RapidIO Block4 Enable Register

02D0 005C

RIO_BLK4_EN_STAT

RapidIO Block4 Enable Status Register

02D0 0060

RIO_BLK5_EN

RapidIO Block5 Enable Register

172

Peripheral Information and Electrical Specifications

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