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TMS570LS3137 Datenblatt(PDF) 43 Page - Texas Instruments

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Teilenummer TMS570LS3137
Bauteilbeschribung  TMS570LS3137 16/32-Bit RISC Flash Microcontroller
PDF  159 Pages
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
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TMS570LS3137 Datenblatt(HTML) 43 Page - Texas Instruments

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AddressWaitstates
DataWaitstates
RAM
AddressWaitstates
DataWaitstates
Flash
0MHz
0MHz
0MHz
0MHz
90MHz
45MHz
0
1
3
0
0
0
135MHz
2
120MHz
1
f
HCLK(max)
f
HCLK(max)
f
HCLK(max)
f
HCLK(max)
TMS570LS3137
www.ti.com
SPNS162.
– SEPTEMBER 2011
3.3
Switching Characteristics over Recommended Operating Conditions for Clock Domains
Table 3-1. Clock Domain Timing Specifications
Parameter
Description
Conditions
Min
Max
Unit
fHCLK
HCLK - System clock frequency
PGE
Pipeline mode
160
MHz
enabled
Pipeline mode
45
MHz
disabled
ZWT
Pipeline mode
180
MHz
enabled
Pipeline mode
45
MHz
disabled
fGCLK
GCLK - CPU clock frequency
fHCLK
MHz
fVCLK
VCLK - Primary peripheral clock
100
MHz
frequency
fVCLK2
VCLK2 - Secondary peripheral clock
100
MHz
frequency
fVCLK3
VCLK3 - Secondary peripheral clock
100
MHz
frequency
fVCLKA1
VCLKA1 - Primary asynchronous
100
MHz
peripheral clock frequency
fVCLKA2
VCLKA2 - Secondary asynchronous
100
MHz
peripheral clock frequency
fVCLKA4
VCLKA4 - Secondary asynchronous
50
MHz
peripheral clock frequency
fRTICLK
RTICLK - clock frequency
fVCLK
MHz
3.4
Wait States Required
Figure 3-1. ZWT Wait States Scheme
As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without
any address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 45MHz in non-pipelined
mode. The flash supports a maximum CPU clock speed of 160MHz in pipelined mode for the PGE Package and
180MHz for the ZWT package, with one address wait state and three data wait states.
The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait
state.
Copyright
© 2011, Texas Instruments Incorporated
Device Operating Conditions
43
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