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TMS570LS3137 Datenblatt(PDF) 72 Page - Texas Instruments

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Teilenummer TMS570LS3137
Bauteilbeschribung  TMS570LS3137 16/32-Bit RISC Flash Microcontroller
PDF  159 Pages
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMS570LS3137 Datenblatt(HTML) 72 Page - Texas Instruments

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TMS570LS3137
SPNS162.
– SEPTEMBER 2011
www.ti.com
Table 4-21. Device Memory Map (continued)
FRAME ADDRESS RANGE
RESPNSE FOR ACCESS TO
FRAME CHIP
FRAME
ACTUA
MODULE NAME
UNIMPLEMENTED LOCATIONS IN
SELECT
SIZE
L SIZE
START
END
FRAME
Cyclic Redundancy Checker (CRC) Module Registers
CRC
CRC frame
0xFE00_0000
0xFEFF_FFFF
16MB
512B
Accesses above 0x200 generate abort.
Peripheral Memories
MIBSPI5 RAM
PCS[5]
0xFF0A_0000
0xFF0B_FFFF
128KB
2KB
Abort for accesses above 2KB
MIBSPI3 RAM
PCS[6]
0xFF0C_0000
0xFF0D_FFFF
128KB
2KB
Abort for accesses above 2KB
MIBSPI1 RAM
PCS[7]
0xFF0E_0000
0xFF0F_FFFF
128KB
2KB
Abort for accesses above 2KB
Wrap around for accesses to
unimplemented address offsets lower
DCAN3 RAM
PCS[13]
0xFF1A_0000
0xFF1B_FFFF
128KB
2KB
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower
DCAN2 RAM
PCS[14]
0xFF1C_0000
0xFF1D_FFFF
128KB
2KB
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower
DCAN1 RAM
PCS[15]
0xFF1E_0000
0xFF1F_FFFF
128KB
2KB
than 0x7FF. Abort generated for
accesses beyond offset 0x800.
Wrap around for accesses to
unimplemented address offsets lower
MIBADC2 RAM
PCS[29]
0xFF3A_0000
0xFF3B_FFFF
128KB
8KB
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
Wrap around for accesses to
unimplemented address offsets lower
MIBADC1 RAM
PCS[31]
0xFF3E_0000
0xFF3F_FFFF
128KB
8KB
than 0x1FFF. Abort generated for
accesses beyond 0x1FFF.
Wrap around for accesses to
unimplemented address offsets lower
N2HET2 RAM
PCS[34]
0xFF44_0000
0xFF45_FFFF
128KB
16KB
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
Wrap around for accesses to
unimplemented address offsets lower
N2HET1 RAM
PCS[35]
0xFF46_0000
0xFF47_FFFF
128KB
16KB
than 0x3FFF. Abort generated for
accesses beyond 0x3FFF.
N2HET2 TU2
PCS[38]
0xFF4C_0000
0xFF4D_FFFF
128KB
1KB
Abort
RAM
N2HET1 TU1
PCS[39]
0xFF4E_0000
0xFF4F_FFFF
128KB
1KB
Abort
RAM
FlexRay TU RAM
PCS[40]
0xFF50_0000
0xFF51_FFFF
128KB
1KB
Abort
Debug Components
CoreSight Debug
Reads return zeros, writes have no
CSCS0
0xFFA0_0000
0xFFA0_0FFF
4KB
4KB
ROM
effect
Cortex-R4F
Reads return zeros, writes have no
CSCS1
0xFFA0_1000
0xFFA0_1FFF
4KB
4KB
Debug
effect
Reads return zeros, writes have no
ETM-R4
CSCS2
0xFFA0_2000
0xFFA0_2FFF
4KB
4KB
effect
Reads return zeros, writes have no
CoreSight TPIU
CSCS3
0xFFA0_3000
0xFFA0_3FFF
4KB
4KB
effect
POM
CSCS4
0xFFA0_4000
0xFFA0_4FFF
4KB
4KB
Abort
Peripheral Control Registers
Reads return zeros, writes have no
FTU
PS[23]
0xFFF7_A000
0xFFF7_A1FF
512B
512B
effect
Reads return zeros, writes have no
HTU1
PS[22]
0xFFF7_A400
0xFFF7_A4FF
256B
256B
effect
72
System Information and Electrical Specifications
Copyright
© 2011, Texas Instruments Incorporated
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