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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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TMS570LS3137 Datenblatt(PDF) 83 Page - Texas Instruments |
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TMS570LS3137 Datenblatt(HTML) 83 Page - Texas Instruments |
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83 / 159 page  TMS570LS3137 www.ti.com SPNS162. – SEPTEMBER 2011 4.13.2 On-Chip SRAM Auto Initialization This microcontroller allows some of the on-chip memories to be initialized via the Memory Hardware Initialization mechanism in the System module. This hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ECC). The MINITGCR register enables the memory initialization sequence, and the MSINENA register selects the memories that are to be initialized. For more information on these registers see the TMS570LS31X/21X Technical Reference Manual (SPNU499). The mapping of the different on-chip memories to the specific bits of the MSINENA registers is shown in Table 4-26. Table 4-26. Memory Initialization ADDRESS RANGE CONNECTING MODULE MSINENA REGISTER BIT # BASE ADDRESS ENDING ADDRESS RAM (PD#1) 0x08000000 0x0800FFFF 0(1) RAM (RAM_PD#1) 0x08010000 0x0801FFFF 0(1) RAM (RAM_PD#2) 0x08020000 0x0802FFFF 0(1) RAM (RAM_PD#3) 0x08030000 0x0803FFFF 0(1) MIBSPI5 RAM 0xFF0A0000 0xFF0BFFFF 12(2) MIBSPI3 RAM 0xFF0C0000 0xFF0DFFFF 11(2) MIBSPI1 RAM 0xFF0E0000 0xFF0FFFFF 7(2) DCAN3 RAM 0xFF1A0000 0xFF1BFFFF 10 DCAN2 RAM 0xFF1C0000 0xFF1DFFFF 6 DCAN1 RAM 0xFF1E0000 0xFF1FFFFF 5 FlexRay RAM RAM is not CPU-Addressable n/a(3) MIBADC2 RAM 0xFF3A0000 0xFF3BFFFF 14 MIBADC1 RAM 0xFF3E0000 0xFF3FFFFF 8 N2HET2 RAM 0xFF440000 0xFF57FFFF 15 N2HET1 RAM 0xFF460000 0xFF47FFFF 3 HET TU2 RAM 0xFF4C0000 0xFF4DFFFF 16 HET TU1 RAM 0xFF4E0000 0xFF4FFFFF 4 DMA RAM 0xFFF80000 0xFFF80FFF 1 VIM RAM 0xFFF82000 0xFFF82FFF 2 RTP RAM 0xFFF83000 0xFFF83FFF n/a FlexRay TU RAM 0xFF500000 0xFF51FFFF 13 Ethernet RAM (CPPI Memory 0xFC520000 0xFC521FFF n/a Slave) (1) The TCM RAM wrapper has separate control bits to select the RAM power domain that is to be auto-initialized. (2) The MibSPIx modules perform an initialization of the transmit and receive RAMs as soon as the multi-buffered mode is enabled. This is independent of whether the application chooses to initialize the MibSPIx RAMs using the system module auto-initialization method. (3) Reserved only. The FlexRay RAM has its own initialization mechanism. Copyright © 2011, Texas Instruments Incorporated System Information and Electrical Specifications 83 Submit Documentation Feedback focus.ti.com: TMS570LS3137 |
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