TMS570LS3137 datasheet(93/159 Pages) TI

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TMS570LS3137

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SPNS162.

– SEPTEMBER 2011

Table 4-31. Interrupt Request Assignments (continued)

Modules

Interrupt Sources

Default VIM Interrupt

Channel

Ethernet

C0_RX_PULSE

HWAG1

HWA_INT_REQ_H

HWAG2

HWA_INT_REQ_H

DCC1

DCC done interrupt

DCC2

DCC2 done interrupt

Reserved

84-87

HWAG1

HWA_INT_REQ_L

HWAG2

HWA_INT_REQ_L

Reserved

90-95

NOTE

Address location 0x00000000 in the VIM RAM is reserved for the phantom interrupt ISR

entry; therefore only request channels 0..94 can be used and are offset by 1 address in the

VIM RAM.

NOTE

The EMIF_nWAIT signal has a pull-up on it. The EMIF module generates a "Wait Rise"

interrupt whenever it detects a rising edge on the EMIF_nWAIT signal. This interrupt

condition is indicated as soon as the device is powered up. This can be ignored if the

EMIF_nWAIT signal is not used in the application. If the EMIF_nWAIT signal is actually used

in the application, then the external slave memory must always drive the EMIF_nWAIT signal

such that an interrupt is not caused due to the default pull-up on this signal.

NOTE

The lower-order interrupt channels are higher priority channels than the higher-order interrupt

channels.

NOTE

The application can change the mapping of interrupt sources to the interrupt channels via the

interrupt channel control registers (CHANCTRLx) inside the VIM module.

System Information and Electrical Specifications

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