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TMS570LS3137 Datenblatt(PDF) 89 Page - Texas Instruments

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Teilenummer TMS570LS3137
Bauteilbeschribung  TMS570LS3137 16/32-Bit RISC Flash Microcontroller
PDF  159 Pages
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
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TMS570LS3137 Datenblatt(HTML) 89 Page - Texas Instruments

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TMS570LS3137
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SPNS162.
– SEPTEMBER 2011
Table 4-28. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3) (continued)
NO
Parameter
Value
Unit
MIN
NOM
MAX
Output hold time, EMIFnWE
-3
0
+3
ns
high to EMIFCS[4:2] high (SS =
1)
18
tsu(EMDQMV-EMWEL)
Output setup time, EMIFBA[1:0]
(WS)*E-3
(WS)*E
(WS)*E+3
ns
valid to EMIFnWE low
19
th(EMWEH-EMDQMIV)
Output hold time, EMIFnWE
(WH)*E-3
(WH)*E
(WH)*E+3
ns
high to EMIFBA[1:0] invalid
20
tsu(EMBAV-EMWEL)
Output setup time, EMIFBA[1:0]
(WS)*E-3
(WS)*E
(WS)*E+3
ns
valid to EMIFnWE low
21
th(EMWEH-EMBAIV)
Output hold time, EMIFnWE
(WH)*E-3
(WH)*E
(WH)*E+3
ns
high to EMIFBA[1:0] invalid
22
tsu(EMAV-EMWEL)
Output setup time,
(WS)*E-3
(WS)*E
(WS)*E+3
ns
EMIFADDR[21:0] valid to
EMIFnWE low
23
th(EMWEH-EMAIV)
Output hold time, EMIFnWE
(WH)*E-3
(WH)*E
(WH)*E+3
ns
high to EMIFADDR[21:0] invalid
24
tw(EMWEL)
EMIFnWE active low width (EW
(WST)*E-3
(WST)*E
(WST)*E+3
ns
= 0)
EMIFnWE active low width (EW
(WST+(EWC*1
(WST+(EWC*1
(WST+(EWC*1
ns
= 1)
6)) *E-3
6))*E
6)) *E+3
25
td(EMWAITH-EMWEH)
Delay time from EMIFnWAIT
3E-3
4E
4E+3
ns
deasserted to EMIFnWE high
26
tsu(EMDV-EMWEL)
Output setup time,
(WS)*E-3
(WS)*E
(WS)*E+3
ns
EMIFDATA[15:0] valid to
EMIFnWE low
27
th(EMWEH-EMDIV)
Output hold time, EMIFnWE
(WH)*E-3
(WH)*E
(WH)*E+3
ns
high to EMIFDATA[15:0] invalid
Table 4-29. EMIF Synchronous Memory Timing Requirements
NO.
Parameter
MIN
MAX
Unit
19
tsu(EMIFDV-EM_CLKH)
Input setup time, read data valid on
1
ns
EMIFDATA[15:0] before EMIF_CLK
rising
20
th(CLKH-DIV)
Input hold time, read data valid on
1.5
ns
EMIFDATA[15:0] after EMIF_CLK
rising
Table 4-30. EMIF Synchronous Memory Switching Characteristics
NO.
Parameter
MIN
MAX
Unit
1
tc(CLK)
Cycle time, EMIF clock EMIF_CLK
15
ns
2
tw(CLK)
Pulse width, EMIF clock EMIF_CLK
5
ns
high or low
3
td(CLKH-CSV)
Delay time, EMIF_CLK rising to
7
ns
EMIFnCS[0] valid
4
toh(CLKH-CSIV)
Output hold time, EMIF_CLK rising to
1
ns
EMIFnCS[0] invalid
5
td(CLKH-DQMV)
Delay time, EMIF_CLK rising to
7
ns
EMIFnDQM[1:0] valid
6
toh(CLKH-DQMIV)
Output hold time, EMIF_CLK rising to
1
ns
EMIFnDQM[1:0] invalid
7
td(CLKH-AV)
Delay time, EMIF_CLK rising to
7
ns
EMIFADDR[21:0] and EMIFBA[1:0]
valid
Copyright
© 2011, Texas Instruments Incorporated
System Information and Electrical Specifications
89
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