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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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TMS570LS3137 Datenblatt(PDF) 62 Page - Texas Instruments |
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TMS570LS3137 Datenblatt(HTML) 62 Page - Texas Instruments |
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62 / 159 page  /NR /1 to /64 OSCIN PLL INTCLK /OD /1 to /8 VCOCLK /R /1 to /32 post_ODCLK /NF /1 to /256 PLLCLK /NR2 /1 to /64 OSCIN PLL#2 INTCLK2 /OD2 /1 to /8 VCOCLK2 /R2 /1 to /32 post_ODCLK2 /NF2 /1 to /256 PLL2CLK fPLLCLK = (fOSCIN / NR) * NF / (OD * R) f PLL2CLK = (fOSCIN / NR2) * NF2 / (OD2 * R2) TMS570LS3137 SPNS162. – SEPTEMBER 2011 www.ti.com 4.6.1.3 Phase Locked Loop (PLL) Clock Modules The PLL is used to multiply the input frequency to some higher frequency. The main features of the PLL are: • Frequency modulation can be optionally superimposed on the synthesized frequency of PLL1. The frequency modulation capability of PLL2 is permanently disabled. • Configurable frequency multipliers and dividers. • Built-in PLL Slip monitoring circuit. • Option to reset the device on a PLL slip detection. 4.6.1.3.1 Block Diagram Figure 4-6 shows a high-level block diagram of the two PLL macros on this microcontroller. PLLCTL1 and PLLCTL2 are used to configure the multiplier and dividers for the PLL1. PLLCTL3 is used to configure the multiplier and dividers for PLL2. Figure 4-6. ZWT PLLx Block Diagram 4.6.1.3.2 PLL Timing Specifications Table 4-11. PLL Timing Specifications PARAMETER MIN MAX UNIT fINTCLK PLL1 Reference Clock frequency 1 f(OSC_SQR) MHz fpost_ODCLK Post-ODCLK – PLL1 Post-divider input 400 MHz clock frequency fVCOCLK VCOCLK – PLL1 Output Divider (OD) input 550 MHz clock frequency fINTCLK2 PLL2 Reference Clock frequency 1 f(OSC_SQR) MHz fpost_ODCLK2 Post-ODCLK – PLL2 Post-divider input 400 MHz clock frequency fVCOCLK2 VCOCLK – PLL2 Output Divider (OD) input 550 MHz clock frequency 62 System Information and Electrical Specifications Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TMS570LS3137 |
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