SPRUG18 datasheet(104/214 Pages) TI

104 / 214 page

TMS320C6474

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

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7.6

Interrupts

7.6.1

Interrupt Sources and Interrupt Controller

The CPU interrupts on the device are configured through the C64x+ Megamodule Interrupt Controller. The

interrupt controller allows for up to 128 system events to be programmed to any of the twelve CPU

interrupt inputs, the CPU exception input, or the advanced emulation logic. Table 7-13 shows the mapping

of system events to the interrupt controller inputs. Event numbers 0-31 correspond to the default interrupt

mapping of the device. The remaining events must be mapped using software. Table 7-14 lists the Chip

Interrupt Controller (CIC) registers. For more details on chip interrupt controller 0-2 (CIC0, CIC1, and

CIC2), see Section 7.6.2.

Table 7-13. Interrupts

EVENT CHANNEL

EVENT

EVENT DESCRIPTION

EVT0

Output of Event Combiner 0 for Events [31:4]

EVT1

Output of Event Combiner 1 for Events [63:32]

EVT2

Output of Event Combiner 2 for Events [95:64]

EVT3

Output of Event Combiner 3 for Events [127:96]

SEMINTn (1)

Semaphore Grant Interrupt

MACINTn (2)

Ethernet MAC Control Interrupt

MACRXINTn (2)

Ethernet MAC Receive Interrupt

MACTXINTn (2)

Ethernet MAC Transmit Interrupt

MACTHRESHn (2)

Ethernet MAC Receive Threshold Interrupt

EMU_DTDMAn (3)

ECM Interrupt for:

1. Host Scan Access

2. DTDMA Transfer Complete

3. AET Interrupt

Unused

Reserved

EMU_RTDXRX

RTDX Receive Complete

EMU_RTDXTX

RTDX Transmit Complete

IDMAINT0

IDMA Channel 0 Interrupt

IDMAINT1

IDMA Channel 1 Interrupt

FSEVT0

Frame Synchronization Event 0

FSEVT1

Frame Synchronization Event 1

FSEVT2

Frame Synchronization Event 2

FSEVT3

Frame Synchronization Event 3

FSEVT4

Frame Synchronization Event 4

FSEVT5

Frame Synchronization Event 5

FSEVT6

Frame Synchronization Event 6

FSEVT7

Frame Synchronization Event 7

FSEVT8

Frame Synchronization Event 8

FSEVT9

Frame Synchronization Event 9

FSEVT10

Frame Synchronization Event 10

FSEVT11

Frame Synchronization Event 11

FSEVT12

Frame Synchronization Event 12

FSEVT13

Frame Synchronization Event 13

(1)

C64x+ Megamodule Core 0, C64x+ Megamodule Core 1, and C64x+ Megamodule Core 2 receive SEMINT0, SEMINT1, and SEMINT2,

respectively.

(2)

EMAC interrupts, MACINTn, MACRXINTn, MACTXINTn, and MACTHRESHn are received by the C64x+ Megamodules, as follows:

•

C64x+ Megamodule Core 0 receives MACINT[0], MACRXINT[0], MACTXINT[0], and MACTHRESH[0]

•

C64x+ Megamodule Core 1 receives MACINT[1], MACRXINT[1], MACTXINT[1], and MACTHRESH[1]

•

C64x+ Megamodule Core 2 receives MACINT[2], MACRXINT[2], MACTXINT[2], and MACTHRESH[2]

(3)

C64x+ Megamodule Core 0, C64x+ Megamodule Core 1, and C64x+ Megamodule Core 2 receive EMU_DTDMA0, EMU_DTDMA1, and

EMU_DTDMA2, respectively.

104

Peripheral Information and Electrical Specifications

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