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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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SPRUG18 Datenblatt(PDF) 107 Page - Texas Instruments |
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SPRUG18 Datenblatt(HTML) 107 Page - Texas Instruments |
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107 / 214 page  TMS320C6474 www.ti.com SPRS552H – OCTOBER 2008 – REVISED APRIL 2011 Table 7-13. Interrupts (continued) EVENT CHANNEL EVENT EVENT DESCRIPTION 126 EMC_CMPA CPU Memory Protection Fault 127 EMC_BUSERR Bus Error Interrupt Table 7-14. Chip Interrupt Controller Registers HEX ADDRESS ACRONYM REGISTER NAME 0288 0000 CIC0 Chip Interrupt Controller 0 Registers 0288 0100 CIC1 Chip Interrupt Controller 1 Registers 0288 0200 CIC2 Chip Interrupt Controller 2 Registers 0288 0300 CIC3 Chip Interrupt Controller 3 Registers 7.6.2 System Event Routing Additional system events are routed to each of the C64x+ Megamodules to provide chip-level events that are not required as CPU interrupts/exceptions to be routed to the interrupt controller as emulation events. Additionally, error-class events or infrequently used events are also routed through the system event router to offload the C64x+ Megamodule interrupt selector. This is accomplished through Chip Interrupt Controllers, CIC[2:0], with one controller per C64x+ Megamodule. This is clocked using CPU/6. The event controllers consist of simple combination logic to provide sixteen events to each C64x+ Megamodule, plus the TPCC. These events are routed to the C64x+ Megamodules for AET purposes, from those TPCC and FSYNC events that are not otherwise provided to each C64x+ Megamodule. The event controllers each include two event combiners to provide two combined events to each C64x+ Megamodule, for use. Each of the 16 event outputs from the controllers can select any of the 64 inputs, or either of the two combined events to pass on to their respective C64x+ Megamodule. Table 7-15 lists the system events that are available to each C64x+ Megamodule through their respective event controllers. Note that n implies the event number matches the C64x+ Megamodule number to which it is routed. Table 7-15. C64x+ Megamodule Chip Interrupt Controller Event List CIC[2:0] EVENT CHANNEL EVENT EVENT DESCRIPTION 0 EVT0 Output of Event Controller 0 for Events [31:2] 1 EVT1 Output of Event Controller 1 for Events [63:32] 2-3 Unused Reserved 4 I2CINT Error Interrupt 5 FSERR1 Error/Alarm Interrupt 1 6 RIOINT7 RapidIO Interrupt 7 7 FSERR2 Error/Alarm Interrupt 2 8 VCPINT Error Interrupt 9 TCPINT Error Interrupt 10 RINT0 McBSP0 Receive Interrupt 11 XINT0 McBSP0 Transmit Interrupt 12 RINT1 McBSP1 Receive Interrupt 13 XINT1 McBSP1 Transmit Interrupt 14 REVT0 McBSP0 Receive EDMA Event 15 XEVT0 McBSP0 Transmit EDMA Event 16 REVT1 McBSP1 Receive EDMA Event 17 XEVT1 McBSP1 Transmit EDMA Event Copyright © 2008–2011, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 107 Submit Documentation Feedback Product Folder Link(s) :TMS320C6474 |
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