SPRUG18 datasheet(183/214 Pages) TI

183 / 214 page

SRIOSGMIIREFCLK(N|P)

TMS320C6474

www.ti.com

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

Table 7-79. RapidIO Control Registers (continued)

HEX ADDRESS

ACRONYM

02D1 4214

SP2_CS_TX

Port 2 Control Symbol Transmit Register

02D1 4218 - 02D1 42FC

Reserved

02D1 4300

SP3_RST_OPT

Port 3 Reset Option CSR

02D1 4304

SP3_CTL_INDEP

Port 3 Control Independent Register

02D1 4308

SP3_SILENCE_TIMER

Port 3 Silence Timer Register

02D1 430C

SP3_MULT_EVNT_CS

Port 3 Multicast-Event Control Symbol Request Register

02D1 4310

Reserved

02D1 4314

SP3_CS_TX

Port 3 Control Symbol Transmit Register

02D1 4318 - 02D2 0FFF

Reserved

02D2 1000 - 02DF FFFF

Reserved

7.18.3 Serial RapidIO Electrical Data/Timing

Serial RapidIO is electrically compliant with the RapidIO

™ Interconnect Specification, Part VI: Physical

Layer 1x/4x LP-Serial Specification, Revision 1.2.

Table 7-80. Timing Requirements for SRIOSGMIIREFCLK(N|P)(1)

(see Figure 7-43)

NO.

PARAMETERS

MIN

MAX

UNIT

tc(SRIOSGMIIREFCLK)

Cycle time, SRIOSGMIIREFCLK(N|P)

3.2

tw(CLKH)

Pulse duration, CLK(N|P) high

0.4C

tw(CLKL)

Pulse duration, CLK(N|P) low

0.4C

tt(CLK)

Transition time, CLK(N|P)

1300

tj(CLK)

Period Jitter (RMS), CLK(N|P)

(1)

C=1/SRIOSGMIIREFCLK(N|P)

Figure 7-43. SRIOSGMIIREFCLK(N|P) Timing

Peripheral Information and Electrical Specifications

183

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