SPRUG18 datasheet(187/214 Pages) TI

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TCK

TDO

TDI/TMS

TMS320C6474

www.ti.com

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

7.20.3 IEEE 1149.1 JTAG

The JTAG interface is used to support boundary scan and emulation of the device. The boundary scan

supported allows for an asynchronous TRST and only the 5 baseline JTAG signals (e.g. no EMU[1:0])

required for boundary scan. Most interfaces on the device follow the Boundary Scan Test Specification

(IEEE1149.1), while all of the SerDes (Antenna Interface, RapidIO, and SGMII) support the AC coupled

net test defined in AC Coupled Net Test Specification (IEEE1149.6).

It is expected that all compliant devices are connected through the same JTAG interface, in daisy-chain

fashion, as per the specification. The JTAG interface uses 1.8-V buffers, compliant with the Power Supply

Voltage and Interface Standard for Nonterminated Digital Integrated Circuit Specification (EAI/JESD8-5).

7.20.3.1 IEEE 1149.1 JTAG Compatibility Statement

For maximum reliability, the C6474 DSP includes an internal pulldown (IPD) on the TRST pin to ensure

that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be

properly initialized when this pin is not routed out. JTAG controllers from Texas Instruments actively drive

TRST high. However, some third-party JTAG controllers may not drive TRST high but expect the use of

an external pullup resistor on TRST. When using this type of JTAG controller, assert TRST to initialize the

DSP after powerup and externally drive TRST high before attempting any emulation or boundary scan

operations.

7.20.3.2 JTAG Electrical Data/Timing

Table 7-85. Timing Requirements for JTAG

(see Figure 7-46)

NO.

PARAMETER

MIN

MAX

UNITS

tc(TCK)

Cycle time, TCK

tw(TCKH)

Pulse width time TCK high

tw(TCKL)

Pulse width time TCK low

td(TCKL-TDOV)

Delay time, TCK low to TDO valid

tsu(TDIV-TCKH)

Setup time, TDI valid before TCK high

tsu(TMSV-TCKH)

Setup time, TMS valid before TCK high

th(TCKH-TDIV)

Hold time, TDI valid after TCK high

th(TCKH-TMSV)

Hold time, TMS valid after TCK high

Figure 7-46. JTAG Timing

Peripheral Information and Electrical Specifications

187

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