AD6674 datasheet(38/97 Pages) AD

38 / 97 page

Data Sheet

AD6674

Rev. C | Page 37 of 96

ADC OVERRANGE AND FAST DETECT

In receiver applications, it is desirable to have a mechanism to

reliably determine when the converter is about to be clipped.

The standard overrange bit in the JESD204B outputs provides

information on the state of the analog input that is of limited

usefulness. Therefore, it is helpful to have a programmable

threshold below full scale that allows time to reduce the gain

before the clip actually occurs. In addition, because input

signals can have significant slew rates, the latency of this

function is of major concern. Highly pipelined converters can

have significant latency. The AD6674 contains fast detect

circuitry for individual channels to monitor the threshold and

assert the FD_A and FD_B pins.

ADC OVERRANGE (OR)

The ADC overrange indicator is asserted when an overrange is

detected on the input of the ADC. The overrange indicator can

be embedded within the JESD204B link as a control bit (when

CSB > 0). The latency of this overrange indicator matches the

sample latency.

The AD6674 constantly monitors the analog input level and

records any overrange condition in any of the eight virtual

converters. For more information on the virtual converters,

refer to Figure 102. The overrange status of each virtual

converter is registered as a sticky bit (that is, it is set until

cleared) in Register 0x563. Clear the contents of Register 0x563

using Register 0x562 by toggling the bits corresponding to the

virtual converter to set and reset the position.

FAST THRESHOLD DETECTION (FD_A AND FD_B)

The fast detect (FD) bit (enabled in the control bits via

whenever the absolute value of the input signal exceeds the

programmable upper threshold level. The FD bit is only cleared

when the absolute value of the input signal drops below the

lower threshold level for greater than the programmable dwell

time. This provides hysteresis and prevents the FD bit from

excessively toggling.

The operation of the upper threshold and lower threshold registers,

along with the dwell time registers, is shown in Figure 97.

The FD_x indicator is asserted if the input magnitude exceeds

the value programmed in the fast detect upper threshold registers,

located in Register 0x247 and Register 0x248. The selected

threshold register is compared with the signal magnitude at the

output of the ADC. The fast upper threshold detection has a

latency of 28. The approximate upper threshold magnitude is

defined by

Upper Threshold Magnitude (dBFS) = 20 log (Threshold

Magnitude/213)

The FD_x indicators are not cleared until the signal drops

below the lower threshold for the programmed dwell time. The

lower threshold is programmed in the fast detect lower thresh-

old registers, located in Register 0x249 and Register 0x24A. The

fast detect lower threshold register is a 13-bit register that is

compared with the signal magnitude at the output of the ADC.

This comparison is subject to the ADC pipeline latency but is

accurate in terms of converter resolution. The lower threshold

magnitude is defined by

Lower Threshold Magnitude (dBFS) = 20 log (Threshold

Magnitude/213)

For example, to set an upper threshold of −6 dBFS, write

0x0FFF to Register 0x247 and Register 0x248; and to set a lower

threshold of −10 dBFS, write 0x0A1D to Register 0x249 and

The dwell time can be programmed from 1 to 65,535 sample

clock cycles by placing the desired value in the fast detect dwell

time registers, located in Register 0x24B and Register 0x24C.

See the Memory Map section (Register 0x245 to Register 0x24C in

Table 45) for more details.

UPPER THRESHOLD

LOWER THRESHOLD

FD_A OR FD_B

DWELL TIME

TIMER RESET BY

RISE ABOVE

LOWER

THRESHOLD

TIMER COMPLETES BEFORE

SIGNAL RISES ABOVE

LOWER THRESHOLD

DWELL TIME

Figure 97. Threshold Settings for FD_A and FD_B Signals

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