AD6674 datasheet(66/97 Pages) AD

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Data Sheet

AD6674

Rev. C | Page 65 of 96

Code Group Synchronization (CGS) and SYNCINB±

Code group synchronization (CGS) is the process by which the

JESD204B receiver finds the boundaries between the 10-bit

symbols in the stream of data. During the CGS phase, the

JESD204B transmit block transmits /K28.5/ characters. The

receiver must locate /K28.5/ characters in its input data stream

using clock and data recovery (CDR) techniques.

The receiver issues a synchronization request by asserting the

SYNCINB± pin of the AD6674 low. The JESD204B Tx begins

sending /K/ characters. After the receiver has synchronized, it

waits for the correct reception of at least four consecutive /K/

symbols. It then deasserts SYNCINB±. The AD6674 then

transmits an ILAS on the following LMFC boundary.

For more information on the CGS phase, refer to the JEDEC

Standard No. 204B (July 2011), Section 5.3.3.1.

The SYNCINB± pin operation can also be controlled by the

SPI. The SYNCINB± signal is a differential LVDS mode signal

by default, but it can also be driven single-ended. For more

information on configuring the SYNCINB± pin operation, refer

to Register 0x572. The SYNCINB± pin can also be configured

to run in CMOS (single-ended) mode by setting Bit 4 in

connect the CMOS SYNCINB signal to Pin 21 (SYNCINB+)

and leave Pin 20 (SYNCINB–) floating.

Initial Lane Alignment Sequence (ILAS)

The ILAS phase follows the CGS phase and begins on the next

LMFC boundary. The ILAS consists of four multiframes, with

an /R/ character marking the beginning and an /A/ character

marking the end. The ILAS begins by sending an /R/ character

followed by 0 to 255 ramp data for one multiframe. On the

second multiframe the link configuration data is sent, starting

with the third character. The second character is a /Q/ character

to confirm that the link configuration data follows. All undefined

data slots are filled with ramp data. The ILAS sequence is never

scrambled.

The ILAS sequence construction is shown in Figure 126. The

four multiframes include the following:



Multiframe 1: Begins with an /R/ character [K28.0] and

ends with an /A/ character (K28.3).



Multiframe 2: Begins with an /R/ character followed by a

/Q/ (K28.4) character, followed by link configuration

parameters over 14 configuration octets (see Table 33), and

ends with an /A/ character. Many of the parameter values

are of the value − 1 notation.



Multiframe 3: Begins with an /R/ character (K28.0) and

ends with an /A/ character (K28.3).



Multiframe 4: Begins with an /R/ character (K28.0) and

ends with an /A/ character (K28.3).

User Data and Error Detection

After the ILAS is complete, the user data is sent. Normally, in a

frame all characters are user data. However, to monitor the frame

clock and multiframe clock synchronization, there is a mechanism

for replacing characters with /F/ or /A/ alignment characters

when the data meets certain conditions. These conditions are

different for unscrambled and scrambled data. The scrambling

operation is enabled by default but can be disabled using the SPI.

For scrambled data, any 0xFC character at the end of a frame is

replaced by an /F/ and any 0x7C character at the end of a

multiframe is replaced with an /A/. The JESD204B Rx checks

for /F/ and /A/ characters in the received data stream and verifies

that they only occur in the expected locations. If an unexpected

/F/ or /A/ character is found, the receiver handles the situation

by using dynamic realignment or asserting the SYNCINB±

signal for more than four frames to initiate a resynchronization.

For unscrambled data, if the final character of two subsequent

frames is equal, the second character is replaced with an /F/ if it

is at the end of a frame, and an /A/ if it is at the end of a multiframe.

Insertion of alignment characters can be modified using the SPI.

The frame alignment character insertion is enabled by default. For

more information on the link controls, see Register 0x571 in the

Memory Map section.

K K R D

D A R Q C

C D

D A R D

D A D

START OF

ILAS

START OF LINK

CONFIGURATION DATA

END OF

MULTIFRAME

START OF

USER DATA

Figure 126. Initial Lane Alignment Sequence

Table 33. AD6674 Control Characters Used in JESD204B

Abbreviation

Control Symbol

8-Bit Value

10-Bit Value, RD1 = −1

10-Bit Value, RD1 = +1

Description

/R/

K28.0

000 11100

001111 0100

110000 1011

Start of multiframe

/A/

K28.3

011 11100

001111 0011

110000 1100

Lane alignment

/Q/

K28.4

100 11100

001111 0010

110000 1101

Start of link configuration data

/K/

K28.5

101 11100

001111 1010

110000 0101

Group synchronization

/F/

K28.7

111 11100

001111 1000

110000 0111

Frame alignment

1 RD is running disparity.

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