AD6674 datasheet(75/97 Pages) AD

75 / 97 page

AD6674

Data Sheet

Rev. C | Page 74 of 96

SYSREF± SETUP/HOLD WINDOW MONITOR

To assist in ensuring a valid SYSREF± capture, the AD6674 has

a SYSREF± setup and hold window monitor. This feature allows

the system designer to determine the location of the SYSREF±

signals relative to the CLK± signals by reading back the amount

of setup/hold margin on the interface through the memory

map. Figure 143 and Figure 144 show both the setup and hold

status values for different phases of SYSREF±. The setup

detector returns the status of the SYSREF± signal before the

CLK± edge and the hold detector returns the status of the

SYSREF± signal after the CLK± edge. Register 0x128 stores the

status of SYSREF± and lets the user know if the SYSREF± signal

was successfully captured by the ADC.

VALID

0xF

0xE

0xD

0xC

0xB

0xA

0x9

0x8

0x7

0x6

0x5

0x4

0x3

0x2

0x1

0x0

REG 0x128[3:0]

CLK±

INPUT

SYSREF±

INPUT

FLIP-FLOP

HOLD (MIN)

FLIP-FLOP

HOLD (MIN)

FLIP-FLOP

SETUP (MIN)

Figure 143. SYSREF± Setup Detector

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