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AD6674 Datenblatt(PDF) 61 Page - Analog Devices

Teilenummer AD6674
Bauteilbeschribung  385 MHz BW IF Diversity Receiver
PDF  97 Pages
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AD6674 Datenblatt(HTML) 61 Page - Analog Devices

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AD6674
Data Sheet
Rev. C | Page 60 of 96
VARIABLE DYNAMIC RANGE (VDR)
The AD6674 features a VDR digital processing block to allow
up to a 14-bit dynamic range to be maintained in a subset of the
Nyquist band. Across the full Nyquist band, a minimum 9-bit
dynamic range is available at all times. This operation is suitable
for applications such as DPD processing. The harmonic perfor-
mance of the receiver is unaffected by this feature. When
enabled, VDR does not contribute loss to the input signal but
operates by effectively changing the output resolution at the
output pins. This feature can be independently controlled per
channel via the SPI.
The VDR block operates in either complex or real mode. In
complex mode, VDR has selectable bandwidths of 25% and 43%
of the output sample rate. In real mode, the bandwidth of
operation is limited to 25% of the output sample rate. The
bandwidth and mode of the VDR operation are selected by
setting the appropriate bits in Register 0x430.
When the VDR block is enabled, input signals that violate a
defined mask (signified by gray shaded areas in Figure 119)
result in the reduction of the output resolution of the AD6674.
The VDR block analyzes the peak value of the aggregate signal
level in the disallowed zones to determine the reduction of the
output resolution. To indicate that the AD6674 is reducing
output, the resolution VDR punish bits and/or a VDR high/low
resolution bit can optionally be inserted into the output data
stream as control bits by programming the appropriate value
into Register 0x559 and Register 0x55A. Up to two control bits
can be used without the need to change the converter resolution
parameter, N. Up to three control bits can be used, but if using
three, the converter resolution parameter, N, must be changed
to 13. The VDR high/low resolution bit can be programmed
into either of the three available control bits and simply
indicates if VDR is reducing output resolution (bit value is a 1),
or if full resolution is available (bit value is a 0). Enable the two
punish bits to give a clearer indication of the available
resolution of the sample. To decode these two bits, see Table 25.
Table 25. VDR Reduced Output Resolution Values
VDR Punish Bits[1:0]
Output Resolution (Bits)
00
14
01
13
10
12 or 11
11
10 or 9
The frequency zones of the mask are defined by the bandwidth
mode selected in Register 0x430. The upper amplitude limit for
input signals located in these frequency zones is −30 dBFS. If
the input signal level in the disallowed frequency zones goes
above an amplitude level of –30 dBFS (into the gray shaded
areas), the VDR block triggers a reduction in the output
resolution, as shown in Figure 119. The VDR block engages and
begins limiting output resolution gradually as the signal
amplitudes increase in the mask regions. As the signal
amplitude level increases into the mask regions, the output
resolution is gradually lowered. For every 6 dB increase in
signal level above −30 dBFS, one bit of output resolution is
discarded from the output data by the VDR block, as shown in
Table 26. These zones can be tuned within the Nyquist band by
setting Bits[3:0] in Register 0x434 to determine the VDR center
frequency (fVDR). The VDR center frequency in complex mode
can be adjusted from 1/16 fS to 15/16 fS in 1/16 fS steps. In real
mode, fVDR can be adjusted from 1/8 fS to 3/8 fS in 1/16 fS steps.
Table 26. VDR Reduced Output Resolution Values
Signal Amplitude Violating Defined
VDR Mask
Output Resolution
(Bits)
Amplitude ≤ −30 dBFS
14
−30 dBFS < amplitude ≤ −24 dBFS
13
−24 dBFS < amplitude ≤ −18 dBFS
12
−18 dBFS < amplitude ≤ −12 dBFS
11
−12 dBFS < amplitude ≤ −6 dBFS
10
−6 dBFS < amplitude ≤ 0 dBFS
9
dBFS
–30
0
INTERMODULATION PRODUCTS < –30dBFS
INTERMODULATION PRODUCTS > –30dBFS
fS
0
fS
Figure 119. VDR Operation—Reduction in Output Resolution



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