AD6674 datasheet(11/97 Pages) AD

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AD6674

Data Sheet

Rev. C | Page 10 of 96

Timing Diagrams

SERDOUT0–

N – 54

N – 53

N – 52

N – 51

N – 1

SAMPLE N

N + 1

APERTURE

DELAY

N – 55

CLK+

CLK–

CLK+

CLK–

SERDOUT0+

SERDOUT1–

SERDOUT1+

SERDOUT2–

SERDOUT2+

SERDOUT3–

SERDOUT3+

ABCD

BCD

ABC

BCD

ABC

BCD

ABC

BCD

CONVERTER0 MSB

CONVERTER0 LSB

CONVERTER1 MSB

CONVERTER1 LSB

ANALOG

INPUT

SIGNAL

SAMPLE N – 55

ENCODED INTO 1

8-BIT/10-BIT SYMBOL

SAMPLE N – 54

ENCODED INTO 1

8-BIT/10-BIT SYMBOL

SAMPLE N – 53

ENCODED INTO 1

8-BIT/10-BIT SYMBOL

Figure 2. Data Output Timing (VDR Mode; L = 4; M = 2; F = 1)

CLK+

CLK–

SYSREF+

SYSREF–

tSU_SR

tH_SR

Figure 3. SYSREF± Setup and Hold Timing

DON’T CARE

SDIO

SCLK

tDH

tCLK

tDS

R/W

A14

A13

A12

A11

A10

D5D4D3D2D1D0

tLOW

tHIGH

CSB

Figure 4. Serial Port Interface Timing Diagram

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