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AD6674 Datenblatt(PDF) 55 Page - Analog Devices |
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AD6674 Datenblatt(HTML) 55 Page - Analog Devices |
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55 / 97 page ![]() AD6674 Data Sheet Rev. C | Page 54 of 96 Chip Application Layer Chip Decimation Ratio DDC Input Type DDC Output Type Bandwidth Per DDC1 No. of Virtual Converters Required Register Settings2 Two DDCs 2 Real Real 19.25%× fS 2 0x200 = 0x22 (two DDCs; I only selected) 0x201 = 0x01 (chip decimate by 2) 0x310, 0x330 = 0x48 (real mixer; 6 dB gain; variable IF; real output; HB2 + HB1 filters) 0x311 = 0x00 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel A) 0x331 = 0x05 (DDC 1 I input = ADC Channel B; DDC 1 Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 Two DDCs 2 Complex Complex 38.5%× fS 4 0x200 = 0x22 (two DDCs; I only selected) 0x201 = 0x01 (chip decimate by 2) 0x310, 0x330 = 0x4B (complex mixer; 6 dB gain; variable IF; complex output; HB1 filter) 0x311, 0x331 = 0x04 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 Two DDCs 4 Complex Complex 19.25% × fS 4 0x200 = 0x02 (two DDCs; I/Q selected) 0x201 = 0x02 (chip decimate by 4) 0x310, 0x330 = 0x80 (complex mixer; 0 dB gain; variable IF; complex outputs; HB2 + HB1 filters) 0x311, 0x331 = 0x04 (DDC I input = ADC Channel A; DDC Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 Two DDCs 4 Complex Real 9.63% × fS 2 0x200 = 0x22 (two DDCs; I only selected) 0x201 = 0x02 (chip decimate by 4) 0x310, 0x330 = 0x89 (complex mixer; 0 dB gain; variable IF; real output; HB3 + HB2 + HB1 filters) 0x311, 0x331 = 0x04 (DDC I input = ADC Channel A; DDC Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 Two DDCs 4 Real Real 9.63% × fS 2 0x200 = 0x22 (two DDCs; I only selected) 0x201 = 0x02 (chip decimate by 4) 0x310, 0x330 = 0x49 (real mixer; 6 dB gain; variable IF; real output; HB3 + HB2 + HB1 filters) 0x311 = 0x00 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel A) 0x331 = 0x05 (DDC 1 I input = ADC Channel B; DDC 1 Q input = ADC Channel B) 0x314, 0x315, 0x320, 0x321 = FTW and POW set as required by application for DDC 0 0x334, 0x335, 0x340, 0x341 = FTW and POW set as required by application for DDC 1 |
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