AD6674 datasheet(29/97 Pages) AD

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AD6674

Data Sheet

Rev. C | Page 28 of 96

THEORY OF OPERATION

The AD6674 has two analog input channels and two JESD204B

output lane pairs. The AD6674 is designed to sample wide

bandwidth analog signals of up to 2 GHz. The AD6674 is

optimized for wide input bandwidth, high sampling rate,

excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth inputs supporting a variety of

user-selectable input ranges. An integrated voltage reference

eases design considerations.

The AD6674 has several functions that simplify the AGC

function in a communications receiver. The programmable

threshold detector allows monitoring of the incoming signal

power using the fast detect bits of the ADC output data stream,

which are enabled and programmed via Register 0x245 through

threshold, the fast detect indicator goes high. Because this

threshold indicator has low latency, the user can quickly lower

the system gain to avoid an overrange condition at the ADC

input.

The Subclass 1 JESD204B-based high speed serialized output

data rate can be configured in one-lane (L = 1) and two-lane

(L = 2) configurations depending upon the sample rate and the

decimation ratio. Multidevice synchronization is supported

through the SYSREF± and SYNCINB± input pins.

ADC ARCHITECTURE

The architecture consists of an input buffered pipelined ADC.

The input buffer is designed to provide a termination imped-

ance to the analog input signal. This termination impedance

can be changed using the SPI to meet the termination needs

of the driver/amplifier. The default termination value is set to

400 Ω. The equivalent circuit diagram of the analog input

termination is shown in Figure 63. The input buffer is

optimized for high linearity, low noise, and low power.

The input buffer provides a linear high input impedance (for

ease of drive) and reduces the kickback from the ADC. The

quantized outputs from each stage are combined into a final

16-bit result in the digital correction logic. The pipelined

architecture permits the first stage to operate with a new input

sample while the remaining stages operate with preceding

samples. Sampling occurs on the rising edge of the clock.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD6674 is a differential buffer. The

internal common-mode voltage of the buffer is 2.05 V. The

clock signal alternately switches the input circuit between

sample mode and hold mode. When the input circuit is switched

into sample mode, the signal source must be capable of charging

the sample capacitors and settling within one-half of a clock cycle.

A small resistor, in series with each input, can help reduce the

peak transient current inserted from the output stage of the

driving source. In addition, low Q inductors or ferrite beads can

be placed on each section of the input to reduce high differen-

tial capacitance at the analog inputs and, thus, achieve the

maximum bandwidth of the ADC. Such use of low Q inductors

or ferrite beads is required when driving the converter front end

at high IF frequencies. Place either a differential capacitor or

two single-ended capacitors on the inputs to provide a matching

passive network. This ultimately creates a low-pass filter at the

input, which limits unwanted broadband noise. For more infor-

mation, refer to the AN-742 Application Note, the AN-827

Application Note, and the Analog Dialogue article “Transformer-

Coupled Front-End for Wideband A/D Converters” (Volume 39,

April 2005) at www.analog.com. In general, the precise values

depend on the application.

For best dynamic performance, match the source impedances

driving VIN+x and VIN−x such that common-mode settling

errors are symmetrical. These errors are reduced by the

common-mode rejection of the ADC. An internal reference

buffer creates a differential reference that defines the span of the

ADC core.

Maximum SNR performance is achieved by setting the ADC

to the largest span in a differential configuration. In the case

of the AD6674, the available span is programmable through

the SPI port from 1.46 V p-p to 2.06 V p-p differential, with

1.70 V p-p differential being the default for the AD6674-1000

and AD6674-750, whereas the default for the AD6674-500 is

2.06 V p-p.

Differential Input Configurations

There are several ways to drive the AD6674, either actively or

passively. However, optimum performance is achieved by

driving the analog input differentially.

For applications where SNR and SFDR are key parameters,

differential transformer coupling is the recommended input

configuration (see Figure 74 and Table 9) because the noise

performance of most amplifiers is not adequate to achieve the

true performance of the AD6674.

For low to midrange frequencies, it is recommended to use a

double balun or double transformer network (see Figure 74) for

optimum performance from the AD6674. For higher

frequencies in the second or third Nyquist zone, it is better to

remove some of the front-end passive components to ensure

wideband operation (see Figure 74 and Table 9).

ADC

0.1µF

BALUN

NOTES

1. SEE TABLE 9 FOR COMPONENT VALUES.

Figure 74. Differential Transformer Coupled Configuration for AD6674

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