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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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AD6674 Datenblatt(PDF) 78 Page - Analog Devices |
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AD6674 Datenblatt(HTML) 78 Page - Analog Devices |
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78 / 97 page  Data Sheet AD6674 Rev. C | Page 77 of 96 Table 40, Table 41, and Table 42 show examples of some of the test modes when inserted at the JESD204B sample input, physical layer (PHY) 10-bit input, and scrambler 8-bit input. UP in the Table 40 to Table 42 represent the user pattern control bits from the memory map register table (see Table 45). Data Link Layer Test Modes The data link layer test modes are implemented in the AD6674 as defined by Section 5.3.3.8.2 in the JEDEC JESD204B specifica- tion. These tests are shown in Register 0x574, Bits[2:0]. Test patterns inserted at this point are useful for verifying the functionality of the data link layer. When the data link layer test modes are enabled, disable SYNCINB± by writing 0xC0 to Register 0x572. Table 40. JESD204B Sample Input for M = 2, S = 2, N΄ = 16 (Register 0x573[5:4] = 'b00) Frame No. Converter No. Sample No. Alternating Checkerboard 1/0 Word Toggle Ramp PN9 PN23 User Repeat User Single 0 0 0 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 0 0 1 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 0 1 0 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 0 1 1 0x5555 0x0000 (x) % 216 0x496F 0xFF5C UP1[15:0] UP1[15:0] 1 0 0 0xAAAA 0xFFFF (x + 1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0] 1 0 1 0xAAAA 0xFFFF (x + 1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0] 1 1 0 0xAAAA 0xFFFF (x + 1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0] 1 1 1 0xAAAA 0xFFFF (x + 1) % 216 0xC9A9 0x0029 UP2[15:0] UP2[15:0] 2 0 0 0x5555 0x0000 (x + 2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0] 2 0 1 0x5555 0x0000 (x + 2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0] 2 1 0 0x5555 0x0000 (x + 2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0] 2 1 1 0x5555 0x0000 (x + 2) % 216 0x980C 0xB80A UP3[15:0] UP3[15:0] 3 0 0 0xAAAA 0xFFFF (x + 3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0] 3 0 1 0xAAAA 0xFFFF (x + 3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0] 3 1 0 0xAAAA 0xFFFF (x + 3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0] 3 1 1 0xAAAA 0xFFFF (x + 3) % 216 0x651A 0x3D72 UP4[15:0] UP4[15:0] 4 0 0 0x5555 0x0000 (x + 4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000 4 0 1 0x5555 0x0000 (x + 4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000 4 1 0 0x5555 0x0000 (x + 4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000 4 1 1 0x5555 0x0000 (x + 4) % 216 0x5FD1 0x9B26 UP1[15:0] 0x0000 Table 41. Physical Layer 10-Bit Input (Register 0x573[5:4] = 'b01) 10-Bit Symbol No. Alternating Checkerboard 1/0 Word Toggle Ramp PN9 PN23 User Repeat User Single 0 0x155 0x000 (x) % 210 0x125 0x3FD UP1[15:6] UP1[15:6] 1 0x2AA 0x3FF (x + 1) % 210 0x2FC 0x1C0 UP2[15:6] UP2[15:6] 2 0x155 0x000 (x + 2) % 210 0x26A 0x00A UP3[15:6] UP3[15:6] 3 0x2AA 0x3FF (x + 3) % 210 0x198 0x1B8 UP4[15:6] UP4[15:6] 4 0x155 0x000 (x + 4) % 210 0x031 0x028 UP1[15:6] 0x000 5 0x2AA 0x3FF (x + 5) % 210 0x251 0x3D7 UP2[15:6] 0x000 6 0x155 0x000 (x + 6) % 210 0x297 0x0A6 UP3[15:6] 0x000 7 0x2AA 0x3FF (x + 7) % 210 0x3D1 0x326 UP4[15:6] 0x000 8 0x155 0x000 (x + 8) % 210 0x18E 0x10F UP1[15:6] 0x000 9 0x2AA 0x3FF (x + 9) % 210 0x2CB 0x3FD UP2[15:6] 0x000 10 0x155 0x000 (x + 10) % 210 0x0F1 0x31E UP3[15:6] 0x000 11 0x2AA 0x3FF (x + 11) % 210 0x3DD 0x008 UP4[15:6] 0x000 |
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