AD6674 datasheet(39/97 Pages) AD

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AD6674

Data Sheet

Rev. C | Page 38 of 96

SIGNAL MONITOR

The signal monitor block provides additional information about

the signal being digitized by the ADC. The signal monitor

computes the peak magnitude of the digitized signal. This

information can be used to drive an AGC loop to optimize the

range of the ADC in the presence of real-world signals.

The results of the signal monitor block can be obtained either

by reading back the internal values from the SPI port or by

embedding the signal monitoring information into the

JESD204B interface as special control bits. A global, 24-bit

programmable period controls the duration of the measure-

ment. Figure 98 shows the simplified block diagram of the

signal monitor block.

FROM

MEMORY

MAP

DOWN

COUNTER

COUNT = 1?

MAGNITUDE

STORAGE

FROM

INPUT

SIGNAL

MONITOR

HOLDING

LOAD

CLEAR

COMPARE

A > B

LOAD

TO SPORT OVER

JESD204B AND

MEMORY MAP

SIGNAL MONITOR

PERIOD REGISTER

(SMPR)

0x271, 0x272, 0x273

Figure 98. Signal Monitor Block

The peak detector captures the largest signal within the

observation period. This period observes only the magnitude of

the signal. The resolution of the peak detector is a 13-bit value,

and the observation period is 24 bits and represents converter

output samples. The peak magnitude is derived by using the

following equation:

Peak Magnitude (dBFS) = 20 log(Peak Detector Value/213)

The magnitude of the input port signal is monitored over a

programmable time period that is determined by the signal

monitor period registers (SMPRs). Only even values of the

SMPR are supported. The peak detector function is enabled by

setting Bit 1 of Register 0x270 in the signal monitor control

activating this mode.

After enabling this mode, the value in the SMPR is loaded into a

monitor period timer that decrements at the decimated clock

rate. The magnitude of the input signal is compared with the

value in the internal magnitude storage register (not accessible

to the user), and the greater of the two is updated as the current

peak level. The initial value of the magnitude storage register is

set to the current ADC input signal magnitude. This comparison

continues until the monitor period timer reaches a count of 1.

When the monitor period timer reaches a count of 1, the 13-bit

peak level value is transferred to the signal monitor holding

through the serial port (SPORT) over the JESD204B interface.

The monitor period timer is reloaded with the value in the

SMPR, and the countdown is restarted. In addition, the

magnitude of the first input sample is updated in the internal

magnitude storage register, and the comparison and update

procedure, as explained previously, continues.

SPORT OVER JESD204B

The signal monitor data can also be serialized and sent over the

JESD204B interface as control bits. These control bits must be

deserialized from the samples to reconstruct the statistical data.

This signal control monitor function is enabled by setting

Bits[1:0] of Register 0x279 and Bit 1 of Register 0x27A.

Figure 99 shows two different example configurations for the

signal monitor control bit locations inside the JESD204B

samples. There are a maximum of three control bits that can be

inserted into the JESD204B samples; however, only one control

bit is required for the signal monitor. Control bits are inserted

from MSB to LSB. If only one control bit is to be inserted (CS = 1),

only the most significant control bit is used (see Configuration 1

and Configuration 2 in Figure 99). To select the SPORT over

JESD204B option, program Register 0x559, Register 0x55A, and

more information on setting these bits.

Figure 100 shows the 25-bit frame data that encapsulates the

peak detector value. The frame data is transmitted MSB first

with five 5-bit subframes. Each subframe contains a start bit

that can be used by a receiver to validate the deserialized data.

Figure 101 shows the SPORT over the JESD204B signal monitor

frame data with a monitor period timer set to 80 samples.

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