AD6674 datasheet(4/97 Pages) AD

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Data Sheet

AD6674

Rev. C | Page 3 of 96

REVISION HISTORY

8/2016—Rev. B to Rev. C

Changes to Figure 1...........................................................................1

Changes to Table 1 ............................................................................5

Changes to Table 5 ............................................................................9

Changes to Table 8 ..........................................................................12

Added Figure 15; Renumbered Sequentially ...............................15

Added Figure 34 ..............................................................................19

Added Figure 53 ..............................................................................23

Changes to Figure 72 ......................................................................27

Changes to Table 10 ........................................................................32

Changes to Input Clock Driver Section .......................................34

Changes to Clock Jitter Considerations Section .........................35

Changes to Setting Up the NCO FTW and POW Section ........48

Changes to JESD204B Overview Section.....................................63

Changes to Figure 123 Caption and Figure 124 ..........................64

Changes to ADC Test Modes Section...........................................76

Added Datapath Soft Reset Section ..............................................80

Changes to Table 45 ........................................................................81

Changes to Ordering Guide...........................................................96

4/2015—Rev. A to Rev. B

Changed SPIVDD Range from 1.8 V to 3.3 V to

1.8 V to 3.4 V ..................................................................Throughout

Changes to General Description Section.......................................4

Changes to Table 1 ............................................................................5

Changes to Table 3 ............................................................................8

Changes to Figure 14 ......................................................................15

Change to Figure 78 Caption.........................................................27

Changes to Table 10 ........................................................................29

Changes to Clock Jitter Considerations Section .........................32

Added Figure 92; Renumbered Sequentially...............................32

Changes to Digital Downconverter (DDC) Section...................37

Changes to Table 17 ........................................................................46

Changes to Table 23 ........................................................................49

Changes to Figure 108 ....................................................................53

Changes to Figure 116 ....................................................................56

Changes to Figure 117 and VDR Complex Mode Section ........57

Changes to Table 45 ........................................................................79

12/2014—Revision A: Initial Version

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