AD6674 datasheet(54/97 Pages) AD

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Data Sheet

AD6674

Rev. C | Page 53 of 96

LOW-PASS

FILTER

REAL

HB1 FIR

LOW-PASS

FILTER

HB1 FIR

COMPLEX TO

REAL ENABLE

90°

0°

–

COMPLEX TO REAL CONVERSION

GAIN STAGE

cos(wt)

sin(wt)

fS/4

I/REAL

0dB

6dB

0dB

6dB

0dB

6dB

0dB

6dB

Figure 110. Complex to Real Conversion Block

DDC EXAMPLE CONFIGURATIONS

Table 23 describes the register settings for multiple DDC example configurations.

Table 23. DDC Example Configurations

Chip

Application

Layer

Chip

Decimation

Ratio

DDC Input

Type

DDC

Output

Type

Bandwidth

Per DDC1

No. of Virtual

Converters

Required

One DDC

Complex

38.5% × fS

0x200 = 0x01 (one DDC; I/Q selected)

0x201 = 0x01 (chip decimate by 2)

0x310 = 0x83 (complex mixer; 0 dB gain;

variable IF; complex outputs; HB1 filter)

0x311 = 0x04 (DDC I input = ADC Channel A;

DDC Q input = ADC Channel B)

0x314, 0x315, 0x320, 0x321 = FTW and POW set

as required by application for DDC 0

One DDC

Complex

19.25% × fS

0x200 = 0x01 (one DDC; I/Q selected)

0x201 = 0x02 (chip decimate by 4)

0x310= 0x80 (complex mixer; 0 dB gain;

variable IF; complex outputs; HB2 + HB1 filters)

0x311= 0x04 (DDC I input = ADC Channel A;

DDC Q input = ADC Channel B)

0x314, 0x315= FTW and POW set as required by

application for DDC 0

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