TMS570LS3137 datasheet(130/159 Pages) TI

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NHET1

NHET2

IOMM mux control signal x

NHET1[1,3,5,7,9,11] / NHET2[8,10,12,14,16,18]

NHET1[1,3,5,7,9,11]

NHET2[8,10,12,14,16,18]

TMS570LS3137

SPNS162.

– SEPTEMBER 2011

www.ti.com

Figure 5-7. N2HET Monitoring

5.4.5.2

Output Monitoring using Dual Clock Comparator (DCC)

N2HET1[31] is connected as a clock source for counter 1 in DCC1. This allows the application to measure

the frequency of the pulse-width modulated (PWM) signal on N2HET1[31].

Similarly, N2HET2[0] is connected as a clock source for counter 1 in DCC2. This allows the application to

measure the frequency of the pulse-width modulated (PWM) signal on N2HET2[0].

Both N2HET1[31] and N2HET2[0] can be configured to be internal-only channels. That is, the connection

to the DCC module is made directly from the output of the N2HETx module (from the input of the output

buffer).

For more information on DCC see Section 4.7.3.

5.4.6

Disabling N2HET Outputs

Some applications require the N2HET outputs to be disabled under some fault condition. The N2HET

module provides this capability via the "Pin Disable" input signal. This signal, when driven low, causes the

N2HET outputs identified by a programmable register (HETPINDIS) to be tri-stated. Please refer to the

TMS570LS31X/21X Technical Reference Manual (SPNU499) for more details on the "N2HET Pin Disable"

feature.

GIOA[5] is connected to the "Pin Disable" input for N2HET1, and GIOB[2] is connected to the "Pin

Disable" input for N2HET2.

130

Peripheral Information and Electrical Specifications

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