SPRUG18 datasheet(147/214 Pages) TI

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Bit0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit0

Bit(n-1)

(n-2)

(n-3)

(n-4)

CLKX

FSX

TMS320C6474

www.ti.com

SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

Table 7-51. Timing Requirements for McBSP as SPI Master: CLKSTP = 10b, CLKXP = 1(1)

(see Figure 7-32)

MASTER

SLAVE

NO.

UNIT

MIN

MAX

MIN

MAX

tsu(DRV-CKXH)

Setup time, DR valid before CLKX high

2 - 18P

th(CKXH-DRV)

Hold time, DR valid after CLKX high

5 + 36P

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

Table 7-52. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI

Master: CLKSTP = 10b, CLKXP = 1(1)

(see Figure 7-32)

MASTER(2)

SLAVE

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

th(CKXH-FXL)

Hold time, FSX low after CLKX high(3)

T - 2

T + 3

td(FXL-CKXL)

Delay time, FSX low to CLKX low(4)

H - 2

H + 3

td(CKXL-DXV)

Delay time, CLKX low to DX valid

-2

18P + 2.8

30P + 17

Disable time, DX high impedance following

tdis(CKXH-DXHZ)

H - 2

H + 3

last data bit from CLKX high

Disable time, DX high impedance following

tdis(FXH-DXHZ)

6P + 3

18P + 17

last data bit from FSX high

td(FXL-DXV)

Delay time, FSX low to DX valid

12P + 2

24P + 17

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(2)

S = Sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)

S = Sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

T = CLKX period = (1 + CLKGDV) * S

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd

L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd

(3)

FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

(4)

FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master

clock (CLKX).

Figure 7-32. McBSP Timing as SPI Master: CLKSTP = 10b, CLKXP = 1

Peripheral Information and Electrical Specifications

147

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