SPRUG18 datasheet(143/214 Pages) TI

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TMS320C6474

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SPRS552H

– OCTOBER 2008 – REVISED APRIL 2011

Table 7-45. Switching Characteristics Over Recommended Operating Conditions for McBSP(1) (2)

(see Figure 7-28)

NO.

MIN

MAX

UNIT

td(CKSH-CKRXH)

Delay time, CLKS high to CLKR/X high for internal CLKR/X

1.4

generated from CLKS input.(3)

tc(CKRX)

Cycle time, CLKR/X

CLKR/X int

10P(4)

tw(CKRX)

Pulse duration, CLKR/X high or

CLKR/X int

C - 1(5)

C + 1(5)

CLKR/X low

td(CKRH-FRV)

Delay time, CLKR high to internal

CLKR int

-2.1

FSR valid

td(CKXH-FXV)

Delay time, CLKX high to internal

CLKX int

-1.7

FSX valid

CLKX ext

1.7

tdis(CKXH-DXHZ)

Disable time, DX high impedance

CLKX int

-3.9

following last data bit from CLKX

CLKX ext

2.1

high

CLKX int

-3.9 +D1(6)

4 + D2(6)

td(CKXH-DXV)

Delay time, CLKX high to DX valid CLKX ext (DXENA = 0)

2.1(6)

9(6)

CLKX ext (DXENA = 1)

2.1 + D1(6)

9 + D2(6)

Delay time, FSX high to DX valid

FSX int

-2.3 + D1(7)

5.6 + D2(7)

td(FXH-DXV)

ONLY applies when in data delay

FSX ext

1.9 + D1(7)

9 + D2(7)

0 (XDATDLY = 00b)mode

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

Minimum delay times also represent minimum output hold times.

(3)

The CLKS signal is shared by both McBSP0 and McBSP1 on this device.

(4)

P = 1/CPU clock frequency, in ns. For example, when running parts at 1000 MHz, use P = 1 ns.

(5)

C = H or L S = sample rate generator input clock = 6P if CLKSM = 1 (P = 1/CPU clock frequency)

S = sample rate generator input clock = P_clks if CLKSM = 0 (P_clks = CLKS period)

H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even

H = (CLKGDV + 1)/2 * S if CLKGDV is odd L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even

L = (CLKGDV + 1)/2 * S if CLKGDV is odd CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the

maximum limit (see (4) above).

(6)

Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 6P, D2 = 12P

(7)

Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 6P, D2 = 12P

Peripheral Information and Electrical Specifications

143

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