DLPA2000 datasheet(31/63 Pages) TI

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7.3.2 Device Startup

• The HOST_IRQ signal is provided to indicated when the system has completed auto-initialization.

• While reset is applied, HOST_IRQ is tri-stated (an external pullup resistor pulls the line high).

• HOST_IRQ remains tri-stated (pulled high externally) until the boot process completes. While the signal is

pulled high, this indicates that the controller is performing boot-up and auto-initialization.

• As soon as possible after the controller boots-up, the controller drives HOST_IRQ to a logic high state to

indicate that the controller is continuing to perform auto-initialization (no real state changes occur on the

external signal).

• The software sets HOST_IRQ to a logic low state at the completion of the auto-initialization process. At the

falling edge of the signal, the initialization is complete.

• The DLPC34xx controller is ready to receive commands through I2C or accept video over the DSI or the

parallel interface only after auto-initialization is complete.

• The controller initialization typically completes (HOST_IRQ goes low) within 500 ms of RESETZ being

asserted. However, this time may vary depending on the software version and the contents of the user

configurable auto initialization file.

(INIT_BUSY)

HOST_IRQ

(with external pullup)

RESETZ

auto-initialization

t0: rising edge of RESETZ; auto-initialization begins

t1: falling edge of HOST_IRQ; auto-initialization is complete

Figure 7-5. HOST_IRQ Timing

7.3.3 SPI Flash

7.3.3.1 SPI Flash Interface

The DLPC34xx controller requires an external SPI serial flash memory device to store the firmware. Follow

the below guidelines and requirements in addition to the requirements listed in the Flash Interface Timing

Requirements section.

The controller supports a maximum flash size of 128 Mb (16 MB). See the DLPC34xx Validated SPI Flash

Device Options table for example compatible flash options. The minimum required flash size depends on the

size of the utilized firmware. The firmware size depends upon a variety of factors including the number of

sequences, lookup tables, and splash images.

The DLPC34xx controller uses a single SPI interface that complies to industry standard SPI flash protocol. The

device will begin accessing the flash at a nominal 1.42-MHz frequency before running at a nominal 30-MHz rate.

The flash device must support these rates.

The controller has two independent SPI chip select (CS) control lines. Ensure that the chip select pin of the

flash device is connects to SPI0_CSZ0 as the controller boot routine is executes from the device connected to

chip select zero. The boot routine uploads program code from flash memory to program memory then transfers

control to an auto-initialization routine within program memory.

The DLPC34xx is designed to support any flash device that is compatible with the modes of operation, features,

and performance as defined in the Additional DLPC34xx SPI Flash Requirements table below Table 7-3, Table

7-4, and Table 7-5.

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