DLPA2000 datasheet(44/63 Pages) TI

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System State

SYSPWR

PROJ_ON (GPIO_8)

VDD (1.1 V)

VDDLP12

(if not ed to VDD)

VDD_PLLM/D (1.1 V)

VCC18 (1.8 V)

VCC_INTF (e.g. 1.8 V)

VCC_FLSH (e.g. 1.8 V)

PARKZ

PLL_REFCLK

RESETZ

HOST_IRQ

2C (activity)

(b)

(c)

Regular operation

Normal

Park

Power supply shutdown

Signals

from PMIC

from other source

(a)

t1:

PROJ_ON goes low to begin the power down sequence.

t2:

The controller finishes parking the DMD.

t3:

RESETZ is asserted which causes HOST_IRQ to be pulled high.

t4:

All controller power supplies are turned off.

t5:

SYSPWR is removed now that all other supplies are turned off.

(a):

I2C activity must stop before PROJ_ON is deasserted (goes low).

(b):

The DMD will be parked within 20 ms of PROJ_ON being deasserted (going low). VDD, VDD_PLLM/D, VCC18, VCC_INITF, and

VCC_FLSH power supplies and the PLL_REFCLK must be held within specification for a minimum of 20 ms after PROJ_ON

is deasserted (goes low). However, 20 ms does not satisfy the typical shutdown timing of the entire chipset. It is therefore

recommended to follow note (c).

(c):

It is recommended that SYSPWR not be turned off for 50 ms after PROJ_ON is deasserted (goes low). This time allows the

DMD to be parked, the controller to turn off, and the PMIC supplies to shut down.

Figure 9-2. Normal Park Power-Down Waveforms

DLPC3420

DLPS232 – OCTOBER 2021

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