DLPA2000 datasheet(5/63 Pages) TI

5 / 63 page

Table 5-2. Parallel Port Input (continued)

PIN(1) (2)

I/O

TYPE(4)

DESCRIPTION

NAME

NO.

PARALLEL RGB MODE

BT656 INTERFACE MODE

(TYPICAL RGB 888)

PDATA_0

PDATA_1

PDATA_2

PDATA_3

PDATA_4

PDATA_5

PDATA_6

PDATA_7

Blue (bit weight 1)

Blue (bit weight 2)

Blue (bit weight 4)

Blue (bit weight 8)

Blue (bit weight 16)

Blue (bit weight 32)

Blue (bit weight 64)

Blue (bit weight 128)

BT656_Data (0)

BT656_Data (1)

BT656_Data (2)

BT656_Data (3)

BT656_Data (4)

BT656_Data (5)

BT656_Data (6)

BT656_Data (7)

(TYPICAL RGB 888)

PDATA_8

PDATA_9

PDATA_10

PDATA_11

PDATA_12

PDATA_13

PDATA_14

PDATA_15

Green (bit weight 1)

Green (bit weight 2)

Green (bit weight 4)

Green (bit weight 8)

Green (bit weight 16)

Green (bit weight 32)

Green (bit weight 64)

Green (bit weight 128)

Unused

(TYPICAL RGB 888)

PDATA_16

PDATA_17

PDATA_18

PDATA_19

PDATA_20

PDATA_21

PDATA_22

PDATA_23

P10

Red (bit weight 1)

Red (bit weight 2)

Red (bit weight 4)

Red (bit weight 8)

Red (bit weight 16)

Red (bit weight 32)

Red (bit weight 64)

Red (bit weight 128)

Unused

3DR

3D reference

•

For 3D applications: left or right 3D reference (left = 1, right = 0). To be

provided by the host. Must transition in the middle of each frame (no

closer than 1 ms to the active edge of VSYNC).

•

If a 3D application is not used, pull this input low through an external

resistor.

(1)

PDATA(23:0) bus mapping depends on pixel format and source mode. See later sections for details.

(2)

Connect unused inputs to ground or pulldown to ground through an external resistor (8 kΩ or less).

(3)

VSYNC and HSYNC polarity can be adjusted by software.

(4)

See Table 5-11 for type definitions.

Table 5-3. DSI Input Data and Clock

I/O

TYPE(2)

DESCRIPTION

NAME

NO.

DCLKN

DCLKP

I/O

DSI LVDS differential clock for DSI interface.

DD0N

DD0P

DD1N

DD1P

DD2N

DD2P

DD3N

DD3P

I/O

Differential data bus for DSI data lane LVDS differential pair inputs 0

through 3.

(support a maximum of 4 input DSI lanes)(1)

RREF

—

DSI reference resistor. RREF is an analog signal that requires a fixed

precision 30-kΩ ±1% resistor connected from this pin to ground when DSI

is used. If DSI is NOT used, leave this pin unconnected and floating.

(1)

Differential data bus 0 (DD0x) is required for DSI operation. The remaining three data lanes are optional and only needed depending

on the implementation and required video bandwidth. Leave any unused DSI LVDS pairs unconnected and floating.

www.ti.com

DLPC3420

DLPS232 – OCTOBER 2021

Submit Document Feedback

Product Folder Links: DLPC3420

DLPA2000 Datenblatt(PDF) 5 Page - Texas Instruments

DLPA2000 Datenblatt(HTML) 5 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datenblatt Download

Link URL