DLPA2000 datasheet(6/63 Pages) TI

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(2)

See Table 5-11 for type definitions.

Table 5-4. DMD Reset and Bias Control

I/O

TYPE(1)

DESCRIPTION

NAME

NO.

DMD_DEN_ARSTZ

DMD driver enable (active high). DMD reset (active low). When

corresponding I/O power is supplied, the controller drives this signal low

after the DMD is parked and before power is removed from the DMD. If

the 1.8-V power to the DLPC34xx is independent of the 1.8-V power to the

DMD, then TI recommends including a weak, external pulldown resistor to

hold the signal low in case DLPC34xx power is inactive while DMD power

is applied.

DMD_LS_CLK

DMD low speed (LS) interface clock

DMD_LS_WDATA

DMD low speed (LS) serial write data

DMD_LS_RDATA

DMD low speed (LS) serial read data

(1)

See Table 5-11 for type definitions.

Table 5-5. DMD Sub-LVDS Interface

I/O

TYPE(1)

DESCRIPTION

NAME

NO.

DMD_HS_CLK_P

DMD_HS_CLK_N

DMD high speed (HS) interface clock

DMD_HS_WDATA_H_P

DMD_HS_WDATA_H_N

DMD_HS_WDATA_G_P

DMD_HS_WDATA_G_N

DMD_HS_WDATA_F_P

DMD_HS_WDATA_F_N

DMD_HS_WDATA_E_P

DMD_HS_WDATA_E_N

DMD_HS_WDATA_D_P

DMD_HS_WDATA_D_N

DMD_HS_WDATA_C_P

DMD_HS_WDATA_C_N

DMD_HS_WDATA_B_P

DMD_HS_WDATA_B_N

DMD_HS_WDATA_A_P

DMD_HS_WDATA_A_N

A10

B10

A11

B11

DMD sub-LVDS high speed (HS) interface write data lanes. The true

numbering and application of the DMD_HS_WDATA pins depend on the

software configuration. See Table 7-8.

(1)

See Table 5-11 for type definitions.

Table 5-6. Peripheral Interface

PIN(1)

I/O

TYPE(2)

DESCRIPTION

NAME

NO.

CMP_OUT

A12

Successive approximation ADC (analog-to-digital converter) comparator output (DLPC34xx Input). To implement, use

a successive approximation ADC with a thermistor feeding one input of the external comparator and the DLPC34xx

controller GPIO_10 (RC_CHARGE) pin driving the other side of the comparator. It is recommended to use the

DLPAxxxx to achieve this function. CMP_OUT must be pulled-down to ground if this function is not used. (hysteresis

buffer)

CMP_PWM

A15

TI internal use. Leave this pin unconnected.

HOST_IRQ(3)

Host interrupt (output)

HOST_IRQ indicates when the DLPC34xx auto-initialization is in progress and most importantly when it completes.

This pin is tri-stated during reset. An external pullup must be included on this signal.

IIC0_SCL(4)

N10

I/O

I2C secondary (port 0) SCL (bidirectional, open-drain signal with input hysteresis): This pin requires an external pullup

resistor. The secondary I2C I/Os are 3.6-V tolerant (high-voltage-input tolerant) and are powered by VCC_INTF (which

can be 1.8, 2.5, or 3.3 V). External I2C pullups must be connected to a host supply with an equal or higher supply

voltage, up to a maximum of 3.6 V (a lower pullup supply voltage does not typically satisfy the VIH specification of the

secondary I2C input buffers).

IIC1_SCL

R11

I/O

TI internal use. TI recommends an external pullup resistor.

IIC0_SDA(4)

I/O

I2C secondary (port 0) SDA. (bidirectional, open-drain signal with input hysteresis): This pin requires an external

pullup resistor. The secondary I2C port is the control port of controller. The secondary I2C I/O pins are 3.6-V tolerant

(high-volt-input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I2C pullups must be

connected to a host supply with an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply

voltage does not typically satisfy the VIH specification of the secondary I2C input buffers).

IIC1_SDA

R10

I/O

TI internal use. TI recommends an external pullup resistor.

DLPC3420

DLPS232 – OCTOBER 2021

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