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6.14 BT656 Interface General Timing Requirements

The DLPC34xx controller input interface supports the industry standard BT.656 parallel video interface. See the appropriate

ITU-R BT.656 specification for detailed interface timing requirements.(2)

MIN

MAX

UNIT

ƒcll

PCLK frequency

1.0

33.5

MHz

tp_clkper

PCLK period

50% reference points

29.85

1000

tp_clkjit

PCLK jitter

Max fclock

See (1)

tp_wh

PCLK pulse duration high

50% reference points

10.0

tp_wl

PCLK pulse duration low

50% reference points

10.0

tp_su

Setup time – PDATA(7:0) before the active edge of

PCLK

50% reference points

3.0

tp_h

Hold time – PDATA(7:0) after the active edge of

PCLK

50% reference points

0.9

Transition time – all signals

20% to 80% reference points

(rising signal)

80% to 20% reference points

(falling signal)

0.2

3.0

(1)

Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒclock – 5.76 ns]. Clock jitter must maintain setup and hold times. BT.656 data

bits must be mapped to the DLPC34xx PDATA bus as shown in Figure 6-9 shows BT.656 bus mode YCbCr 4:2:2 source PDATA (23:0)

mapping.

(2)

The BT.656 interface accepts 8-bits per color, 4:2:2 YCbCr data encoded per the industry standard through PDATA(7:0) on the active

edge of PCLK. See Figure 6-9.

Bus assignment mapping

PDATA(7:0) of the input pixel data bus

Data bit mapping on controller pin

n/a

Figure 6-9. BT.656 Interface Mode Bit Mapping

6.15 DSI Host Timing Requirements

These timing requirements describe specific host minimum values that are higher than those specified in the MIPI standards.

It is critical for proper operation that the host meet these minimum timing requirements for specified MIPI parameters. The

decoded DSI data must also follow all Section 6.12.

MIN

MAX

UNIT

Clock lane

Frequency

235

MHz

Data lane

Effective data rate

160

470

Mbps

Number of data lanes

Selectable

lanes

tHS-PREPARE+ tHS-ZERO

During a LP to HS transition, the time that

the transmitter drives the HS-0 state prior to

transmitting the synchronization sequence

80-MHz to 94-MHz HS

clock

565

95-MHz to 235-MHz HS

clock(1)

465(2)

tHS-SETTLE

Time interval during which the HS receiver

ignores any data lane HS transitions,

starting from the beginning of THS-PREPARE;

the HS receiver ignores any data lane

transitions before the minimum value, and

responds to any data lane transitions after

the maximum value

80-MHz to 94-MHz HS

clock

565(3)

95-MHz to 235-MHz HS

clock

465(3)

(1)

Example: At 172 MHz and tHS-PREPARE = 51.46 ns → 51.46 ns + tHS-ZERO ≥ 465 ns. Therefore tHS-ZERO ≥ 413.54 ns.

(2)

Minimum values are higher than those required by the MIPI standard. tHS-PREPARE must be within the MIPI specified range.

(3)

Maximum values are higher than those required by the MIPI standard.

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