DLPA2000 datasheet(48/63 Pages) TI

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10 Layout

10.1 Layout Guidelines

For a summary of the PCB design requirements for the DLPC34xx controller see PCB Design Requirements for

TI DLP Pico TRP Digital Micromirror Devices. Some applications (such as high frame rate video) may require the

use of 1-oz (or greater) copper planes to manage the controller package heat.

10.1.1 PLL Power Layout

Follow these recommended guidelines to achieve acceptable controller performance for the internal PLL.

The DLPC34xx controller contains two internal PLLs which have dedicated analog supplies (VDD_PLLM,

VSS_PLLM, VDD_PLLD, and VSS_PLLD). At a minimum, isolate the VDD_PLLx power and VSS_PLLx ground

pins using a simple passive filter consisting of two series ferrite beads and two shunt capacitors (to widen

the spectrum of noise absorption). It’s recommended that one capacitor be 0.1 µF and one be 0.01 µF. Place

all four components as close to the controller as possible. It’s especially important to keep the leads of the

high frequency capacitors as short as possible. Connect both capacitors from VDD_PLLM to VSS_PLLM and

VDD_PLLD to VSS_PLLD on the controller side of the ferrite beads.

Select ferrite beads with these characteristics:

• DC resistance less than 0.40 Ω

• Impedance at 10 MHz equal to or greater than 180 Ω

• Impedance at 100 MHz equal to or greater than 600 Ω

The PCB layout is critical to PLL performance. It is vital that the quiet ground and power are treated like analog

signals. Therefore, VDD_PLLM and VDD_PLLD must be a single trace from the DLPC34xx controller to both

capacitors and then through the series ferrites to the power source. Make the power and ground traces as short

as possible, parallel to each other, and as close as possible to each other.

DLPC3420

DLPS232 – OCTOBER 2021

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DLPA2000 Datenblatt(PDF) 48 Page - Texas Instruments