DLPA2000 datasheet(50/63 Pages) TI

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10.1.2 Reference Clock Layout

The DLPC34xx controller requires an external reference clock to feed the internal PLL. Use either a crystal or

oscillator to supply this reference. The DLPC34xx reference clock must not exceed a frequency variation of ±200

ppm (including aging, temperature, and trim component variation).

Figure 10-2 shows the required discrete components when using a crystal.

PLL_REFCLK_I

PLL_REFCLK_O

RFB

CL1

CL2

Crystal

CL = Crystal load capacitance (farads)

CL1 = 2 × (CL – Cstray_pll_refclk_i)

CL2 = 2 × (CL – Cstray_pll_refclk_o)

where:

•

Cstray_pll_refclk_i = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_i.

•

Cstray_pll_refclk_o = Sum of package and PCB stray capacitance at the crystal pin associated with the controller pin pll_refclk_o.

Figure 10-2. Required Discrete Components

10.1.2.1 Recommended Crystal Oscillator Configuration

Table 10-1. Crystal Port Characteristics

PARAMETER

NOM

UNIT

PLL_REFCLK_I TO GND capacitance

1.5

PLL_REFCLK_O TO GND capacitance

1.5

Table 10-2. Recommended Crystal Configuration

PARAMETER (1) (2)

RECOMMENDED

UNIT

Crystal circuit configuration

Parallel resonant

Crystal type

Fundamental (first harmonic)

Crystal nominal frequency

MHz

Crystal frequency tolerance (including accuracy, temperature, aging and trim sensitivity) ±200

PPM

Maximum startup time

1.0

Crystal equivalent series resistance (ESR)

120 (max)

Crystal load

RS drive resistor (nominal)

100

RFB feedback resistor (nominal)

MΩ

CL1 external crystal load capacitor

See equation in Figure 10-2 notes

CL2 external crystal load capacitor

See equation in Figure 10-2 notes

PCB layout

A ground isolation ring around the

crystal is recommended

(1)

Temperature range of –30°C to 85°C.

(2)

The crystal bias is determined by the controllers VCC_INTF voltage rail, which is variable (not the VCC18 rail).

DLPC3420

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