DLPA2000 datasheet(43/63 Pages) TI

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(c)

SYSPWR

PROJ_ON (GPIO_8)

VDD (1.1 V)

Signals

from PMIC

from other source

VDDLP12 (if not tied to VDD)

VDD_PLLM/D (1.1 V)

VCC18 (1.8 V)

VCC_INTF (e.g. 1.8 V)

VCC_FLSH (e.g. 1.8 V)

PLL_REFCLK

HOST_IRQ

2C (activity)

RESETZ

Pre-Initial-

ization

Regular Operation

Power

Startup

(a)

(b)

(d)

(e)

Initialization

PARKZ

System State

t0:

SYSPWR applied to the PMIC. All other voltage rails are derived from SYSPWR.

t1:

All supplies reach 95% of their specified nominal value. Note HOST_IRQ may go high sooner if it is pulled-up to a different

external supply.

t2:

Point where RESETZ is deasserted (goes high). This indicates the beginning of the controller auto-initialization routine.

t3:

HOST_IRQ goes low to indicate initialization is complete.

(a):

VDDLP12 must be powered on after VDD if it is supplied from a separate source.

(b):

PLL_REFCLK is allowed to be active before power is applied.

(c):

PLL_REFCLK must be stable within 5 ms of all power being applied. For external oscillator applications this is oscillator

dependent, and for crystal applications this is crystal and controller oscillator cell dependent.

(d):

PARKZ must be high before RESETZ releases to support auto-initialization. RESETZ must also be held low for at least 5 ms

after the power supplies are in specification.

(e):

I2C activity cannot start until HOST_IRQ goes low to indicate auto-initialization completes.

Figure 9-1. System Power-Up Waveforms

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