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DLPA2000 Datenblatt(PDF) 20 Page - Texas Instruments

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Teilenummer DLPA2000
Bauteilbeschribung  DLPC3420 Display Controller
PDF  63 Pages
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Hersteller  TI [Texas Instruments]
Direct Link  http://www.ti.com
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DLPA2000 Datenblatt(HTML) 20 Page - Texas Instruments

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6.12 Parallel Interface Frame Timing Requirements
See Section 11.1.3 for additional information
MIN
MAX
UNIT
tp_vsw
Pulse duration – default VSYNC_WE high
50% reference points
1
lines
tp_vbp
Vertical back porch (VBP) – time from the active edge of
VSYNC_WE to the active edge of HSYNC_CS for the first
active line(1)
50% reference points
2
lines
tp_vfp
Vertical front porch (VFP) – time from the active edge of the
HSYNC_CS following the last active line in a frame to the active
edge of VSYNC_WE(1)
50% reference points
1
lines
tp_tvb
Total vertical blanking – the sum of VBP and VFP (tp_vbp +
tp_vfp)
50% reference points
See (1)
lines
tp_hsw
Pulse duration – default HSYNC_CS high
50% reference points
4
128
PCLKs
tp_hbp
Horizontal back porch (HBP) – time from the active edge of
HSYNC_CS to the rising edge of DATAEN_CMD
50% reference points
4
PCLKs
tp_hfp
Horizontal front porch (HFP) – time from the falling edge of
DATAEN_CMD to the active edge of HSYNC_CS
50% reference points
8
PCLKs
(1)
The minimum total vertical blanking is defined by the following equation: tp_tvb(min) = 6 + [8 × Max(1, Source_ALPF / DMD_ALPF)]
lines
where:
SOURCE_ALPF = Input source active lines per frame
DMD_ALPF = Actual DMD used lines per frame supported
VSYNC_WE
HSYNC_CS
DATAEN_CMD
tp_vsw
1 Frame
tp_vbp
tp_vfp
HSYNC_CS
DATAEN_CMD
tp_hsw
1 Line
tp_hfp
tp_hbp
PDATA(23/15:0)
P0
PCLK
P1
P2
P3
P
n-2
P
n-1
Pn
(This diagram assumes the VSYNC
active edge is the rising edge)
(This diagram assumes the HSYNC
active edge is the rising edge)
Figure 6-7. Parallel Interface Frame Timing
DLPC3420
DLPS232 – OCTOBER 2021
www.ti.com
20
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Product Folder Links: DLPC3420



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