DLPA2000 datasheet(45/63 Pages) TI

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t2 t3

System State

SYSPWR

PROJ_ON (GPIO_8)

VDD (1.1 V)

VDDLP12

(if not ed to VDD)

VDD_PLLM/D (1.1 V)

VCC18 (1.8 V)

VCC_INTF (e.g. 1.8 V)

VCC_FLSH (e.g. 1.8 V)

PARKZ

PLL_REFCLK

RESETZ

HOST_IRQ

2C (activity)

Regular operation

Fast

Park

Power supplies collapse

(a)

(b)

Signals

from PMIC

from other source

t1:

A fault is detected (in this example the PMIC detects a UVLO condition) and PARKZ is asserted (goes low) to tell the controller to

initiate a fast park of the DMD.

t2:

The controller finishes the fast park procedure.

t3:

RESETZ is asserted which puts the controller in a reset state which causes HOST_IRQ to be pulled high.

t4:

Eventually all power supplies that were derived from SYSPWR collapse.

(a):

VDD, VDD_PLLM/D, VCC18, VCC_INITF, and VCC_FLSH power supplies and the PLL_REFCLK must be held within

specification for a minimum of 32 µs after PARKZ is asserted (goes low).

(b):

VCC18 must remain in specification long enough to satisfy DMD power sequencing requirements defined in the DMD datasheet.

Also see the DLPAxxxx datasheets for more information.

Figure 9-3. Fast Park Power-Down Waveforms

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