DLPA2000 datasheet(42/63 Pages) TI

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9 Power Supply Recommendations

9.1 PLL Design Considerations

It is acceptable for the VDD_PLLD and VDD_PLLM to be derived from the same regulator as the core VDD.

However, to minimize the AC noise component, apply a filter as recommended in the PLL Power Layout section.

9.2 System Power-Up and Power-Down Sequence

Although the DLPC34xx controller requires an array of power supply voltage pins (for example, VDD, VDDLP12,

VDD_PLLM/D, VCC18, VCC_FLSH, and VCC_INTF), if VDDLP12 is tied to the 1.1-V VDD supply (which is

assumed to be the typical configuration), then there are no restrictions regarding the relative order of power

supply sequencing to avoid damaging the DLPC34xx controller (this remains true for both power-up and power-

down scenarios). The controller requires no minimum delay time between powering-up and powering-down the

individual supplies if the VDDLP12 is tied to the 1.1-V VDD supply.

However, if the VDDLP12 pin is not tied to the VDD supply, then the VDDLP12 pin must be powered-on only

after the VDD supply is powered-on. And in a similar sequence, the VDDLP12 pin must be powered-off before

the VDD supply is powered-off. If the VDDLP12 pin is not tied to VDD, then the VDDLP12 pin and VDD supply

pins must be powered-on or powered-off within 100 ms of each other.

Although there is no risk of damaging the DLPC34xx controller when the above power sequencing rules are

followed, these additional power sequencing recommendations must be considered to ensure proper system

operation:

• To ensure that the DLPC34xx controller output signal states behave as expected, all controller I/O supplies

are encouraged to remain applied while VDD core power is applied. If VDD core power is removed while the

I/O supply (VCC_INTF) is applied, then the output signal states associated with the inactive I/O supply go to

a high impedance state.

• Because additional power sequencing rules may exist for devices that share the supplies with the DLPC34xx

controller (such as the PMIC and DMD), these devices may force additional system power sequencing

requirements.

Figure 9-1, Figure 9-2, and Figure 9-3 show the DLPC34xx power-up sequence, the normal PARK power-down

sequence, and the fast PARK power-down sequence of a typical DLPC34xx system.

When the VDD core power is applied, but I/O power is not applied, the controller may draw additional leakage

current. This leakage current does not affect the normal DLPC34xx controller operation or reliability.

Note

During a Normal Park it is recommended to maintain SYSPWR within specification for at least 50 ms

after PROJ_ON goes low. This is to allow the DMD to be parked and the power supply rails to safely

power down. After 50 ms, SYSPWR can be turned off. If a DLPA200x is used, it is also recommended

that the 1.8-V supply fed into the DLPA200x load switch be maintained within specification for at least

50 ms after PROJ_ON goes low.

DLPC3420

DLPS232 – OCTOBER 2021

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DLPA2000 Datenblatt(PDF) 42 Page - Texas Instruments